論文

This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to 18F2 footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to 26 × and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.

Current overshoot during a set operation has significant impacts on the ON conductance and reliability of resistive change devices such as atom switches. We break the set operation into three steps: incubation, transition, and settling. We clarify their contributions to the determinations of the ON conductance of the atom switch. The variation in the transition time causes a significant variation in the ON conductance. On the basis of the ON conductance distribution, the median of the transition time of 1 ns and its distribution are revealed. © 2014 The Japan Society of Applied Physics.

Cu-alloy active-electrode coupled with Ru-alloy inert electrode is proposed to improve the ON-state reliability of nonvolatile Cu atom switch. The high rupture temperature (T-{r}<400^{\circ}{\rm C}) of the nanometer-scale Cu bridge with high thermal resistance (R-{\rm th}) is realized by the Cu(AlTi)-alloy without increasing programming current. The anti-Cu diffusive Ru(Ta) alloy contributes to improve the retention of the ON-state at 150^{\circ}{\rm C} and endurance to {<}{10}4 cycles. The metallurgical prescription on the electrodes is a key to improve the stability of the nanometer-scale conducting bridge while keeping the switching power low. © 1963-2012 IEEE.

A practical approach to oxygen compensation is investigated to improve a resistive change characteristic of NiO films. The stoichiometry of a physical vapor deposited NiO (PVD-NiO) is changed by post-plasma-oxidation (PPO) process at 350 °C. The PPO process eliminates oxygen vacancies and compensates for a loss of oxygen during Cu back-end-of-line (BEOL) process, which results in a lower forming voltage and a higher OFF/ON resistance ratio. The PPO also improves the surface roughness of the PVD-NiO film, reducing a cell-to-cell variation of the forming voltage. The developed NiO resistance random-access memory (ReRAM) integrated in Cu-BEOL coupled with the PPO process is applicable for realizing a low-power and stable resistive switch. © 2011 The Japan Society of Applied Physics.

Switching voltage variation of a Cu atom switch (AS) is improved to σ =9.5% by adjusting the buffer oxidation state and electrode surface roughness. The complementary AS (CAS) connects two Cu lines at each edge and is composed of a dual-layered electrolyte of oxidized Ti buffer metal/polymer solid electrolyte. A sufficiently oxidized Ti buffer layer prevents both Cu oxidation and Ti diffusion during the fabrication processes, reducing the OFF-state leakage current and making the ON/OFF current ratio high. A dry cleaning process reduces the Cu electrode surface roughness, tightening the set voltage distribution and enabling the use of a low programming voltage, 1.8 V. A large-scale crossbar switch block consisting of CASs has been operated by the improved switches.

Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability. © 2007 IEEE.

We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.

In this work, we present very low temperature boron (B) and phosphorus (P) activation technique in amorphous (α) -Ge using nickel (Ni)- and cobalt (Co)-induced crystallization. Ni and Co not only crystallize an α-Ge film, they also facilitate activation of the respective B and P atoms in the α-Ge during the crystallization process at temperatures as low as 360 °C. The feasibility of the low temperature activation technique has been demonstrated for a Ge gate electrode in a Si P-channel metal-oxide-semiconductor field-effect transistor using Schottky Ni (or Co) silicide source/drain. © 2008 American Institute of Physics.

Low temperature (<350°C) growth of germanium (Ge) on silicon dioxide (SiO2) is demonstrated using a diborane pretreatment technique. Using SiH4 and B2 H6 precursors, Si 1-x Bx layers are deposited on SiO2 to seed the chemical vapor deposition growth of Ge films. In the SiH4: B 2 H6 system, the binary deposition mechanism of the Si1-x Bx film is explained by the "enhancement" model. In situ doping of Ge films is also investigated. In situ boron activation is achieved during the crystallization of the Ge films at 310°C. Device applicability of the doped Ge film growth on oxide is demonstrated in a low temperature (350°C) Si p-channel metal-oxide-semiconductor field-effect transistor, in which the Ge layer is used as a gate electrode. The low temperature Ge growth technique can be used for low thermal budget processes, e.g., monolithic three-dimensional integrated circuits. © 2010 The Electrochemical Society.

A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current-voltage characteristics with high selectivity of 105, which originates from the staircase barrier height in the layers. The two control lines connected to the varistors realize multiple fan-outs of the crossbar switch without select transistors. The 50 sf ×20 crossbar switch block is demonstrated, where the atom switch is placed at each cross point and programmed through the varistors. The developed via-switch crossbar switch is a strong candidate for achieving energy-efficient nonvolatile field-programmable gate array in the Internet-of-Things applications.

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34-1.2 V operating voltage and 12 μA/MHz active current (or 4.5 μW/MHz active power). Furthermore, the sleep current is as low as 0.4 μA when a body bias voltage is applied to the SOTB.

An improvement mechanism of the OFF-state lifetime in a complementary atom switch (CAS) is investigated by detecting a time-dependent stress voltage transition between two atom switches. The CAS consists of two bipolar-resistive-change elements connected in series with opposite direction, which are applicable for a nonvolatile crossbar switch routing signals. In the OFF-state, one switch is biased to the forward (turn-on) direction and the other to reverse (turn-off ) during the crossbar switch operation. It is revealed that the switch elements do not only share the voltage stress with each other, but also mitigate the stress voltage of the forward-biased one by the reverse-biased one. The complementary sharing of the stress voltage in the two atom switches results in enlarging the OFF-state lifetime of the CAS, which is essential for keeping the crossbar switch reliability high.

In this work, we investigate a low temperature boron (B) and phosphorus (P) activation in amorphous (α) -Ge using metal-induced crystallization technique. Eight candidates of metals (Pd, Cu, Ni, Au, Co, Al, Pt, and Ti) are used to crystallize the α-Ge at a low temperature. Resistivity measurement, transmission electron microscopy, and x-ray diffraction analyses reveal behaviors of the metal-induced dopant activation process using the metals reacting with α-Ge. It is revealed that Co achieves the highest B and P activation ratio in Ge below 360 °C with a slow diffusion rate. This method can be utilized to activate gate, source, and drain of transistors on upper layers in three-dimensional integrated circuits, where low temperature processing is critical. © 2009 American Institute of Physics.

Lanthanum fluoride thin films were prepared on silica glass substrates by a sol-gel method using trifluoroacetic acid (TFA) as a fluorine source. A coating solution was produced from lanthanum acetate and trifluoroacetic acid dissolved in 2-propanol. Triuoroacetate gel films were formed by spin coating the sol, which were converted to LaF3 thin films by heat-treatment at 300-500°C for 10min. The formation of LaF3 is considered to result from the reaction between lanthanum ions and the fluorine species generated by the decomposition of trifluoroacetate ions at elevated temperatures. The film fired at 300°C had a smooth surface with a grain size of 30nm. Cracks and voids were only observed in the films fired at 400 and 500°C. The films fired at 300 and 400°C exhibited transmittance of greater than 90% in the visible region.

The plasma-etching technology presented in this paper is for fabricating highly reliable Cu dual damascene interconnects (DDI) with organic low-k film through modification of the in situ etched surface during low-k etching. Nitrogen-based plasma with oxygen and high-molecular-weight fluorocarbon gas (C > 2) chemically modifies the sidewall surface of the etched low-k film, changing it into the carbon nitride with fluorocarbon-polymer passivation from the etching gas. After wet cleaning, the fluorocarbon-polymer is removed selectively, leaving a carbon nitride modified layer (CNL) on the sidewall. The CNL has been found to suppress Cu diffusion into the low-k film. A stacked barrier structure of conventional barrier metal and CNL is expected to have high tolerance to Cu diffusion. Combining a dual-hard-mask etching sequence with the CNL modification, Cu DDIs with organic low-k film were fabricated with high yield. © 2005 IEEE.

The impact of porous low-k films on circuit performance in GHz operation was investigated using high-speed circuits in 65nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore- stacking (MPS) SiOCH films, local low-k/Cu structures (M2-M5) with effective dielectric constants (Keff) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with Keff = 3.4. The interline capacitance (C int), measured using an LCR meter at ̃100 kHz, was reduced by 12% from Keff = 3.4 to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ̃1.5GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2GHz static random access memory (SRAM) with Keff = 2.9 provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in Vddmin, or eventually widening the SRAM operation margin. The porous low-k impact on GHz operation is demonstrated for the first time. © 2009 The Japan Society of Applied Physics.

This paper reports Atom switch technology featuring Cu nanometer-scale conducting bridge in a solid-electrolyte. The switch exhibits resistance-switching, which is originated from Cu electrolysis through the solid-electrolyte. Three types of device structure of Atom switches such as two-terminal device, Complementary Atom Switch (CAS) and Diode-inserted Complementary Atom Switch (DCAS) are reviewed with the object of the routing switch application to directly replace the conventional Complementary Metal-Oxide Semiconductor (CMOS) switch element, realizing the low-power, nonvolatile programmable logic.

In this work, we present very low temperature boron activation technique in amorphous (α)-Ge using Ni-induced crystallization. Ni not only successfully crystallize α-Ge film, it also facilitates activation of the respective boron atoms in the α-Ge during the crystallization process at temperatures as low as 360°C. The feasibility of the low temperature activation technique has successfully been demonstrated for a Ge gate electrode in a Si PMOSFET using Schottky Ni silicide source/drain. ©The Electrochemical Society.

The NanoBridge-FPGA, a field programmable gateway array incorporating NEC's original NanoBridge metal atom migration-type switch, offers higher power efficiency and faster processing speed while achieving excellent durability against radiation and high temperature. That combination of reduced power consumption and increased performance makes the NanoBridge-FPGA suitable for application in a wide spectrum of fields. Featuring higher power efficiency than a CPU, an FPGA is a group of integrated circuits that facilitate hardware (circuit configuration) switching using semiconductor switches and memory modules. The new NanoBridge FPGA ramps up that power efficiency of the FPGA by replacing these semiconductor switches and memory modules with the space-saving NanoBridge. This paper discusses the operating principle of the NanoBridge, the internal construction of the NanoBridge-FPGA, and compares its performance with commercially available FPGAs.