Published papers

A robust Cu dual-damascene (DD) interconnect has been developed in a low-density (LD) SiOCH film with a low- ksidewall protection layer (SPL) made of plasmapolymerized divinylsiloxane-benzocyclobuten (p-BCB, k = 2.7). A thinned Ta/TaN barrier-metal (BM) structure combined with the low-kSPL was implemented. The SPL covering the DD sidewall in the LD-SiOCH film secures the spacing between the lines and vias, and makes low- ksurface smooth which enhances the BM coverage on the DD sidewalls. As a result, the leakage yield against via misalignment and the insulating reliability such as time-dependent dielectric breakdown between the DDIs, particularly with vias, are improved. With our special p-BCB SPL, the BM was able to be thinned to half as thick as the conventional one, reducing resistances of the vias and the line and the interconnect RC delay without any degradation in the via electromigration reliability. The combination of the low-k SPL with the thin BM is a key for scaled-down robust LSIs with Cu DDIs in low-kdielectrics. © 2006 IEEE.

A static timing analysis (STA) tool for a 28nm atomswitch FPGA (AS-FPGA) is introduced to validate the signal delay of an application circuit before implementation. High accuracy of the STA tool is confirmed by implementing a practical application circuit on the 28nm AS-FPGA. Moreover, dramatic improvement of delay and power is demonstrated in comparison with a previous 40nm AS-FPGA.

Abstract MOS capacitors fabricated on substrates with doping concentrations as high as 1018 cm−3 were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μs. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.

Abstract A 100 nm wide superconducting niobium (Nb) interconnect was fabricated by a 300 mm wafer process for Cryo-CMOS and superconducting digital logic applications. A low pressure and long throw sputtering was adopted for the Nb deposition, resulting in good superconductivity of the 50 nm thick Nb film with a critical temperature (Tc) of 8.3 K. The interconnects had a titanium nitride (TiN)/Nb stack structure, and a double-layer hard mask was used for the dry etching process. The exposed area of Nb film was minimized to decrease the effects of plasma damage during fabrication and atmosphere. The developed 100 nm wide and 50 nm thick Nb interconnect showed good superconductivity with a Tc of 7.8 K and a critical current of 3.2 mA at 4.2 K. These results are promising for Cryo-CMOS and superconducting digital logic applications in the 4 K stage.

Abstract A nonvolatile resistive switching of NanoBridgeTM (NB) at 4 K has been demonstrated for realizing the Quantum-classical interface (QCI), in which the challenging of reset operation at cryogenic temperature is successfully achieved. The set voltage of the NB is increased with decreasing temperature, saturated around 150 K and to be 2.55 V at 4 K. The on-state resistances tuned at 1 k–5 kΩ show small temperature dependence down to 4 K due to high residual resistivity. The increased reset current of the NB at 4 K is compensated by the process optimization with thermal engineering and the increased I dsat of the select transistor at 4 K, resulting in stable switching. The low-power QCI featuring NBs is a strong candidate for controlling a large number of qubits at cryogenic temperature.

Physical and chemical properties of plasma-polymerized SiOCH films were investigated using ring-type siloxane monomers with several kinds of side-chain chemicals, and a design principle of the material and plasma-process was derived to obtain a porous SiOCH film of k<2.5 with sub-nanometer-scaled porous structure framed by the original ring siloxane backbone. Here, the backbone siloxane structure is fixed as a six-membered Si-O ring of the 0.35 nmφ, and no progen gas and no post-cure-process were utilized. It was found that unsaturated hydrocarbon side chains such as vinyl increase the deposition rate, and the original monomer structure tends to be kept, reducing the dielectric constant with the porous structure. Large alkyl groups increase the hydrocarbon content in the film as well as the deposition rate. The low radio-frequency power plasma with high precursor concentration also helps the original chemical structure to be preserved. The best solution is to use the ring-type siloxane with both of the vinyl (unsaturated hydrocarbon) and the large alkyl (saturated hydrocarbon) under the low-power plasma condition with the high partial pressure of the precursor. The plasma-polymerized porous SiOCH film is a strong candidate for the low-k film in scale-down 4532 nm node ultralarge-scaled integrated interconnects featured by the simple and low-cost fabrication processes. © 2007 The Electrochemical Society.

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2/CF4/O 2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-depleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication. © 2008 IEEE.

Metal fluoride films were prepared from trifluoroacetate sols by a spin-coating method. Effects of preparation conditions on the deposition of fluoride films have been examined in order to control the thickness and the refractive index of the films. It was suggested that the fluoride was formed by the thermal decomposition of the trifluoroacetate sols generating gaseous phases such as (CF3CO)2O, CO and CO2. This reaction mechanism seemed to largely effect the deposition of the fluoride films in terms of the formation of pores. Characteristics of the fluoride films could be changed by varying the heat treatment. The refractive index of the MgF2 films decreased with increasing heating temperature, which might result from the increased porosity of the films. Drying the film before the heat treatments was effective in the control of the refractive index.

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at Vid = 1 mV and VCM = 0.7 V with VDD = 1.2 V and fs = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ.

The performance and reliability of Cu/Low-κ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-κ damascene interconnect is crucial for the high reliability and performance. © 2004 IEEE.

Low-temperature characterization of electrical transport on atom switches has been performed to clarify operation and conducting mechanisms. The low resistive (ON) state (< 400 Ω) shows metallic conduction accompanied with a high residual resistance. In the high resistive (OFF) state (> 108), the resistance exponentially increases with decreasing temperature due to Poole-Frenkel conduction. In the intermediate range (105-107 Ω), the resistance has small temperature dependence since the electron tunneling via Cu residues in a solid electrolyte is dominant. The polymer solid electrolyte enables the complete collection of the Cu residues without degrading the electrolyte, resulting in forming-free operation and a high ON/OFF conductance ratio. © 2012 IEEE.

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations. © 2007 IEEE.

We demonstrate high performance Ge N+ /P and P+ /N junction diodes at sub- 380 °C. Very low resistivity (2.2× 10 -4 cm) and shallow (92 nm) junction with high degree of dopant activation are achieved especially in N+ /P junction formed at 360 °C on Ge epitaxially grown on Si using complementary metal-oxide semiconductor process compatible-metal (Co) induced dopant activation technique. Excellent diode characteristics having ∼2× 104 on/off ratio and high forward current density (221 A cm2 for N+ /P and 135 A cm2 for P+ /N at ∫ Vf ∫=2 V) are obtained in N+ /P and P+ /N junction diodes fabricated at 380 °C on bulk Ge with a surface passivated layer [Ge O 2 +low temperature chemical vopor deposition Si O2 (LTO)] isolation. © 2008 American Institute of Physics.

© 2015 IEEE. To break the tradeoff relationship between fast and low-voltage programming of a Cu atom switch, the effect of the composition in the AlTi oxide buffer layer placed on a Cu electrode is investigated. To improve the voltage dependence of time-to-ON-state, namely, switching slope (SS), the Cu ionization rate is increased by changing the composition ratio of the AlTi oxide buffer. An Al0.5Ti0.5Oy buffer leads to an extremely steep SS of 56 mV/decade by eliminating metallic Al residue on the Cu electrode. This buffer enables fast (10 ns) and low-voltage ( ∼ 2 V) programming, as demonstrated in a 1-Mbit array. Cycle endurance (> 103 cycles) with a high ON/OFF resistance ratio ( > 104) was also confirmed. The steep SS technology is indispensable for conducting bridges used in a low-power nonvolatile field-programmable gate array.

The performance of CMOS circuits is critically affected by the increased resistivity of the substrate and the well at cryogenic temperatures, yet a reliable model of cryogenic conductivity in highly-doped Si remains lacking. We propose a model based on variable-range hopping conduction that successfully reproduced the measured n-well conductance of lightly compensated Si down to 4.3 K. The Fermi level is accurately estimated by considering donor ionization due to compensating acceptors and screening effects by hopping electrons. The model provides a physically grounded framework for understanding cryogenic conductivity in highly-doped Si that will contribute to more reliable designs of cryo-CMOS circuits.

A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff=~109). The cryogenic characteristics of copper interconnects in the back end of the line (BEOL), including line and via resistances, capacitances, and Joule-heating effect (JHE) are accurately assessed. The interconnect and via resistances decrease with temperature due to a reduction of electron-phonon scattering, resulting in resistances that are 75% and 20% lower at 4.2K compared to those at room temperature(RT). No significant change in inter-line capacitance and no severe JHE are observed in the Cu BEOL at 4.2K. The developed cell libraries for Simulation Program with Integrated Circuit Emphasis (SPICE) model and the technology file, which includes RC interconnect parameters, enable precise design of CMOS circuits at 4.2K. This results in a demonstrated +18.3% increase in speed or -16% reduction in power consumption for ring-oscillator (ROSC) at 4.2K, aligning well with the simulation results obtained from the developed model.

Researchers have demonstrated a highly energy-efficient MCU core using an ultra-low-voltage silicon-on-thin-buried-oxide (SOTB) CMOS technology. The SOTB transistor realizes high performance even at low voltages and ultra-low leakage current, as the variability in threshold voltage is small owing to the fully depleted silicon-on-insulator channel with a low impurity concentration. The SOTB transistor also enables an adaptive threshold voltage control by applying a body-bias voltage. The reported MCU fetches the instruction from an external ROM through a 3.3-V I/O circuit.

© 2019 The Japan Society of Applied Physics. An atom-switch field-programmable gate array (AS-FPGA) uses a simple crossbar switch structure for signal routing. An AS-crossbar switch enables a shorter delay thanks to single-stage routing and the low capacitance of the AS, unlike a routing block which uses multi-stage multiplexers in a conventional static random access memory FPGA. However, the output of a crossbar switch has a variable load capacitance for different fan-outs when the application circuit is mapped on an AS-FPGA. The buffer driving capability for the crossbar switch needs to be carefully designed since there is a trade-off relationship between energy and delay. An optimized buffer reduces the energy-delay product (EDP) of the AS-crossbar switch by 22.3% compared with a non-optimized buffer.

© 2017 The Japan Society of Applied Physics. Logic cell architecture on nanobridge-based field-programmable gate array (NB-FPGA) is investigated in terms of cell area and signal delay. Areadelay product is minimized when the cluster size is 4 and the segment length is 4, because of small area and small capacitance of nanobridge (NB). 1.34' logic density improvement and 15% energy saving, compared to the previous NB-FPGA with cluster size = 2, are demonstrated by implementing an application of a lightweight block cipher.

© 2016 The Japan Society of Applied Physics. For the first time, an area-efficient nonvolatile carry chain combining look-up tables and a pass-transistor-logic-based adder is newly developed using complementary atom switches without additional CMOS circuits. A proposed tristate switch composed of three pairs of complementary atom switches selects one of "0", "1", and the "carryfiin" signal as the input of a common multiplexer for both a look-up table and an adder. The developed nonvolatile carry chain achieves the reductions of 20% area, 17% delay, and 17% power consumption, respectively, in comparison with a conventional nonvolatile carry chain using dedicated CMOS gates.