論文

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

We are developing field-programmable gate arrays (FPGAs) with a new non-volatile switch called via-switch. In via-switch FPGAs (VS-FPGAs), the via-switches required for reconfiguration are placed in the routing layer so that the entire transistor layer can be utilized for computing, and higher implementation density can be achieved compared to conventional SRAM FPGAs. Furthermore, since arithmetic units and memories for computing can be placed under the via-switch crossbar for routing, large-scale parallel operations can be realized where the memory and the arithmetic unit are adjacent to each other. These features enable operation with high energy efficiency. This article reports 65 nm prototype fabrication results and predicted the performance of the VS-FPGA designed for AI applications. We also present the developed application mapping flow and crossbar programming method. The VS-FPGA closes the gap between FPGA and application-specific integrated circuits (ASIC) with the performance advantage of the via-switch and via-switch copy scheme for FPGA-to-ASIC migration, contributing to the expansion of the FPGA usage.

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6 × logic density, 1.5 × energy efficiency, and 1.4 × operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

The authors demonstrate a field-programmable gate array (FPGA) based on NanoBridge, a novel resistive-change switch. NanoBridge, which is integrated in the back end of line (BEOL), features a high on/off conductance ratio, weak temperature dependence of its resistance, nonvolatility, endurance against soft errors, and a small footprint. In place of static RAM (SRAM) and a pass transistor, NanoBridge is utilized as a configuration switch in the FPGA. In this article, the authors evaluate the NanoBridge-based FPGA (NB-FPGA) for applications in harsh environments. Specifically, they implemented NB-FPGA in a humanoid robot and compared its performance with that of the conventional FPGA. Results showed that NB-FPGA exhibits small variation in performance over a wide range of temperature, from-55 to 150 °C, and has high immunity for fluctuations in the power supply voltage.

In this paper, we describes the ON-state reliability of a nonvolatile solid-electrolyte switch for a programmable logic device (PLD). The ON-state requirement for this application is different from that of a Cu via or an interconnect, since the pulsed-AC current is applied to the switch when the voltage changes in the interconnect. We experimentally demonstrate a recovering phenomenon in the migration under AC stress and propose an appropriate ON-state resistance of 800ω to satisfy the requirement for a current density criterion that goes beyond the 28-nm technology node (hp28). The ON-state duration of the crossbar switch under the pulsed-AC current of 1 GHz is estimated to be over 10 years at an ambient of 150 °C. © 2011 The Japan Society of Applied Physics.

Opportunities and challenges of atom switch featuring Cu nanometer-scale conducting bridge in the solid-electrolyte are discussed with comparing the other emerging memories. Atom switch having the high on/off conductance ratio is suitable to directly replace the conventional CMOS switch element, realizing the low-power, nonvolatile programmable logic. Reliability challenges of the atom switch are also discussed in the view point of the stabilization of the on- and off-states. © The Electrochemical Society.

A polymer solid-electrolyte (PSE) switch has been embedded in a 90-nm-node CMOS featuring a forming-less programming and extremely high on/off ratio of 105. A fast programming of 10 ns is also demonstrated for 50-nmφ 1 k-b array by introducing the PSE switches integrated with a fully logic compatible process below 350 °C. A high free volume in the PSE is supposed to result in the smooth formation of the Cu bridge without destroying the electrolyte, thereby also resulting in forming-less programming and high breakdown voltage. High disturbance reliability (T50; 50% fail) is extracted to be over 10 years at operation condition. The improved switching characteristics enable us to accurately program the crossbar circuit in a practical scale (32 × 32) without cell transistors. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic. © 2011 IEEE.

An add-on-type, Pb(Zr,Ti)O3 (PZT) metal-insulator- (MIM) capacitor on Al multilevel interconnects is developed for embedded FeRAM devices, concluding that the oxygen-doping into the ruthenium (Ru) electrodes is crucial for obtaining large remnant polarization under a limited process temperature below 450°C. The oxygen-doped, Ru bottom-electrode with a granular structure reduces the PZT sputtering temperature below 450°C to obtain the ferroelectric perovskite-phase. On the other hand, oxygen doping into the Ru top-electrode suppresses the reductive damage at the interface between the top-electrode and the PZT, keeping the leakage current low. The PZT MIM capacitor with these oxygen-doped, Ru electrodes exhibits the remnant polarization of 21 μC/cm2 on the Al multilevel interconnects with no degradation of the interconnect reliability, thus applicable to the embedded FeRAM in 0.25 μm-CMOS logic LSIs. © 2005 IEEE.

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k = 2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k = 2.9) or porous (k = 2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O 2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multihard-mask process for the DD structure in porous SiOCH film with no exposure to O 2-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond. © 2006 IEEE.

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter (φ) vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-φ vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation. © 2009 IEEE.

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k = 2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k = 2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 Ω was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasmapolymerized benzocyclobuten liner (k = 2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability. © 2006 IEEE.

In this work we have investigated Ni- or Au-induced crystallization and the lateral crystallization of planar amorphous germanium (α-Ge) on silicon dioxide at 360°C without the deleterious effects of thermally induced self-nucleation. Subsequently, single crystalline Ge growth has been achieved on SiO2 by making dimension of α-Ge line to be smaller than the size of grains formed using Ni- and Au-induced lateral crystallizations at 360°C. This method can be used to form the channel region of the MOS devices in upper layers of the three-dimensional integrated circuits at low temperatures. © 2008 American Institute of Physics.

This letter describes a newly established design framework with the layered architecture of processing elements (PEs) exploiting high-level synthesis and its evaluation results. The design framework was developed for intelligent sensor nodes of Internet of Things applications that collaborate with cloud systems, in which small footprint and low power consumption were major concerns. The design framework consists of four layered structure of PE architecture with the extended database management function of a high-level synthesis tool. We investigated the dependencies of resource consumption on the granularity of coarse grained function definitions using the extended database management function of CyberWorkBench. The evaluation results showed that small footprint was achieved especially with dynamically reconfigurable technique.

A set/reset switching model of Cu atom switch based on electrolysis is newly proposed. A nanometer-thick solid electrolyte gives a high electric field of 3.3 MV/cm in the solid electrolyte at 2 V, enabling an ionization of Cu and a formation of Cu bridge. It is revealed that the switching voltage depends on the resistance of electrolyte, where the modified Faraday's law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance. The proposed simple compact model is useful for estimating the resistance of the Cu atom switch programmed by any conditions.

Single-event effects (SEEs) of atom switches (ASs) embedded on 40-nm complementary metal-oxide-semiconductor (CMOS) are investigated with both heavy-ion and pulsed laser irradiation. In the evaluation of an AS-based field-programmable gate array (AS-FPGA), ASs show immunity against the irradiation and there is no change of the state of ASs both in a cross-bar switch and memory in lookup tables (LUTs). ASs are not supposed to make any single-event transient (SET) noise when the ions hit. However, the CMOS layer shows SETs, and new approaches are proposed to solve the SET in CMOS, especially for AS-FPGA application.

Alkaline earth and rare-earth fluoride thin films were prepared on silica glass substrates by a sol-gel process using trifluoroacetic acid (TFA) as a fluorine source. Homogeneous solutions were obtained by stirring a mixture of alkaline earth or rare-earth metal acetates, TFA and H2O, dissolved in isopropanol. The solutions were spin-coated and heated at 300-800°C. The fluoride thin films were obtained by heat treatment around 400°C in air. The crystallization behavior, the surface morphology, and the optical properties of the films depended on the heating temperature as well as the chemical species of the metal ions.

We propose a self-selected smallest set-voltage cell (4S-cell) to realize three-fold improvement of the set-voltage (V set) variability of Cu atom switches. In the cell, switches are connected in parallel and the switch with the smallest V set is automatically selected, resulting in smaller V set variability. For practical application, a split-electrode structure is introduced. The 4S-cells of 2-in-1 by using a split electrode without any increase in cell area reduced the 6σ of V set with an equivalent σV set of 28 mV. The developed 4S-cell enables very-large-scale integration of atom switches for embedded memory and routing switch applications used in ultra-low-power systems-on-chips for wireless sensor node applications.

A diode-inserted complementary atom switch with two resistive-change junctions coupled with the diode-inserted gate is proposed. The atom switch serves the nonvolatile resistive-change junction, where the two atom switches are connected in series with opposite direction and transfer or cutoff the signals. The gate is placed between them through the diode, where back-end-of-the-line--{\rm Ta}-{{2}}{\rm O}-{5{-}x}- diode is directly stacked on the two of atom switches, achieving high rectifying separation of the gate. The developed device realizes the three-terminal operation and potentially enables to replace the CMOS routing switch composed of SRAM and transmission gate with nonvolatility. © 1963-2012 IEEE.

Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLK) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Ω at 0.28 μmØ with keeping large tolerance of misalignment up to 0.1 μm. © 2006 IEEE.