論文

© 2020 IEEE. In this paper, a digital-to-resistance converter (DRC) with automatic offset calibration circuits is proposed. This circuit is used to evaluate the dynamic performance of resistive sensor readout circuits. The proposed DRC consists of a digital-to-analog converter, an analog multiplier, a fixed-value reference resistor, and current sources. A wide-range resistance changing at high frequency is achieved with the proposed DRC. In order to minimize the resistance error caused by the offset voltage of op-amps, an automatic offset calibration method is proposed. This developed prototype DRC achieved 96.3 dB dynamic range, 56.1 dB SNDR at 10kHz, and a maximum operating frequency is 100kHz.

© 2020 IEEE. This paper presents a discrete-time based approach for frequency modulated charge pumps with synchronized controller. In order to handle the varying frequency, this paper first introduced a method to calculate the output voltage of an open-loop charge pump with predefined frequencies, which is improved from a fixed frequency open-loop model verified in previous research. Then a closed-loop model is proposed for synchronized frequency controllers. An algorithm is hence created from the closed-loop model to simulate the output of charge pumps. The simulation result shows a competitive accuracy and much faster speed when comparing it with transistor level simulations. Overall, this paper demonstrated its value in terms of modeling the frequency modulated charge pumps and hence assisted the top-down design flow.

© 2019 IEEE. In this paper, a new readout method for a 2-D cross-point resistive sensor array with an opamp-less interface circuit is proposed. To avoid the readout inaccuracy caused by nonidealities of an opamp in the conventional readout circuit, our proposed circuit does not use any opamps. A switch resistance calibration technique is also proposed to remove effectively the negative effects of switch nonidealities, which bring high readout accuracy and wide scalability of a target resistive array. To evaluate the readout accuracy in the proposed method, simulation is carried out and the readout error less than 0.06% with 16-bit ADCs in 32×32 resistive array is achieved.

© 2018 IEEE This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator. The TDC is used to measure the fractional part of oscillation period, which realize a high resolution and conversion rate with moderate oscillation frequency. Proposed fractional period estimation technique reduce the required number of TDC and save power consumption. A prototype system was developed and 23 ppm resolution of resistance change at conversion rate of 5kSps was experimentally demonstrated.

© 2020 IEEE. This paper proposes a method to separate distortions of the input signal, amplifier, and analog-to-digital converter (ADC), which are cascaded blocks in the testing of an analog front-end system. The proposed technique extends the stimulus error identification and removal (SEIR) method to separate the low-quality input test signal, the nonlinearity of amplifier and ADC. The system model was built by using MATLAB/Simulink, and the nonlinearity of the input signal with distortion, amplifier, and ADC were successfully separated. With a 12-bit ADC, the estimation error of each block is less than 1 LSB in the simulation, and the proposed method was verified by measurement. The relations between the estimation error, calculation cost and each parameter in the proposed method are systematically studied.

© 2020 IEEE. This paper presents a wide-dynamic-range high-resolution time-domain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept, which allows a virtual delay line extension, is applied to achieve high resolution down to 1 ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1 ns to 12 ns allow on the one hand on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. On the other hand, delay stage mismatch calibration. The concept of this paper is evaluated through both simulation and hardware by a custom-designed PCB using commercially available components. An HDL state machine operates as control logic on a generic FPGA. The presented concept is highly suitable for on-chip integration.

© 2018 European Microwave Association. This paper presents a technique to efficiently transfer power to devices regardless of their angle and position by using multi-coil transmitter with magnetic resonance coupling. The magnetic field at receiver coil can be arbitrary controlled by changing the phase of transmitter switching signal. The optimum phase can be determined by reversely transmitting signal from receiver to transmitter and detecting the phase of induced voltage of each transmitter coil. The effectiveness of proposed technique is demonstrated by electro-magnetic field simulation and measurements.

© 2018 IEEE. This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

© 1993-2012 IEEE. To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

© 2018 IEEE. A multi-transmitter wireless power transfer system with magnetic resonance coupling at 6.78MHz is presented. The switching phase of transmitter is controlled by a reverse signal transfer and optimum phase decision technique. The experimental results demonstrate the tracking ability of receiver coil angle change.

© 2019 IEEE. This paper describes a high-resolution, highly linear, low power amp-less sensor interface. A Wheatstone-bridge with ΔΣ-modulated digitally controlled variable resistor is proposed. The proposed bridge is automatically balanced by successive approximation (SA) of the digitally controlled resistor, which can eliminate power consuming amplifiers and ADCs. To overcome conversion speed limitation caused by settling time of each SA step, the output differential voltage of the bridge is shorted in advance to the comparison phase of each SA step. A developed prototype system achieved 9.68 bit resolution in target resistance range of three orders of magnitude and conversion speed improvement by 66%.