Published papers

In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparatorbased wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.

This paper presents a fast response wireless power delivery system with open loop dynamic transmitter voltage scaling technique to keep power efficiency in wide load range. In this technique, according to change of receiver side power consumption, the driving voltage of the transmitter (TX) coil is properly adjusted to control transmission power. The transmitting power and switching loss can be reduced in proportion to the square of the driving voltage. Therefore, it can improve power efficiency. To enhance power control speed, the driving voltage is not locally regulated but automatically determined by the feedback loop of the total WPT system. Fabricated test chips in 180-nm LDMOS process achieved maximum power efficiency of 50.9% when the output power is 0.5W. The output power ranges from 0.03W to 0.5W. The output voltage ripple is kept within 3.5% even when the output power is abruptly changed by one order of magnitude.

This paper presents the influence of metal sheet near the coils of inductively coupled wireless power delivery system. Experiments and electro-magnetic field simulation shows the influence of various kind of metal sheets and sheet positions on the power efficiency and peak frequency shift. The tradeoff between the power efficiency and shielding ability is also discussed.

A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option. © 2013 IEEE.

Recently, many applications have emerged that use wireless power delivery technology. A new standard "Qi" [1] has been established for battery operated portable devices. The rechargeable battery acts as a power buffer and shields the rapid load variation. Therefore, the requirement of the response to load variation is not so stringent and time constant of the power control loop is longer than several tens of milliseconds. Several hundred kHz band is chosen for switching frequency to reduce the power loss and frequency modulation (FM) [2] or pulse-width modulation (PWM) [3] are used for power control because of their relaxed in-band spurious emission regulation. © 2012 IEEE.

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions. © 2006 IEEE.

This paper presents intermittently operating RF frontend for proximity wireless communication with wireless power supply. To realize power scalability of the RF frontend, intermittent operation is performed by switching the bias of the amplifier. Quick startup circuit is proposed to accelerate the charging time to a decoupling capacitor. The fabricated test chip in 65nm CMOS occupies 0.075mm2. The 3dB bandwidth of amplifier ranges from 1.8GHz to 7.2GHz and current consumption is 8mA. The startup time of the circuit is 5ns.

This paper presents a low power DT sigma-delta modulator for wide variety of sensor application using a ring amplifier for SC-integrator. The topology is a second order modulator with single-bit quantizer. Dead-zone effect of the ring amplifier in oversampling ADC is discussed. The fabricated test chip in 65nm CMOS process achieved SNDR of 62dB and 1MHz signal band at sampling frequency of 102.4MHz. The power consumption is 1mW and FoM is 483fJ/conv.step.

This paper presents a fence-type virtual short stub loaded UWB antenna coupler which has broadband and steep cutoff characteristics at both the lower and upper cutoff frequency. The fence-type short stub consists of a top and bottom metal layers of FR4 substrate and Through Holes (THs) connecting layers. Thanks to this geometry, resonance and anti-resonance occur at various frequencies in several signal paths. The size of the antenna is 1cm × 1cm. The simulation result of coupling coefficient parameter (S21) is higher than -20dB from 6.2GHz to 10.4GHz (4.2GHz bandwidth) when the distance between two couplers is 1cm.

This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

This paper presents a wireless solid-state drive (SSD) system for future applications of large volume storage in mobile devices or data centers. The wireless interface in the developed system consists of an inductive-coupling power link with a fast transmitting power control and high-speed data links with transmission line couplers (TLCs). The wireless power link can deliver 1W from the host side to the SSD side. The full duplex wireless data interface achieved raw data rate of 1.6Gbps/link. The error correction block for NAND flash memory system can also correct the error in wireless data links. The data link has tolerance to the interference from the power link, and both the data and power links show the waterproof property of the system.

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.

In this paper, we propose a control method in a wireless power transmission that targets small battery-less devices. Dynamic period switching of PRS-PWM (Pseudo Random Sequence - Pulse Width Modulation) with run length limiting technique has been developed to break through the tradeoff between transient response speed, rectified voltage ripple, and spurious emission. Developed wireless power transmission system has achieved ripple reduction by 44%, response speed of 70μs, and spurious reduction by 15.6dB.

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated. © 2010 IEEE.

A single-inductor dual-output wireless power delivery system for small size battery-less NAND flash memory card is presented. The power delivery system uses two rectifiers connected to a single inductor which is synchronously switched by pseudo-random-sequence PWM signal with induced AC voltage. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 % and maximum total transmitting power of 0.5 W. The test chips were designed and fabricated using 0.18um-CMOS with high-voltage LDMOS option.

Heavier wire harnesses decrease the fuel efficiency of vehicles. The number of wires has increased sharply with presently over one hundred electronic control units (ECUs). Connectors also add to the weight (Fig. 30.6.1(a)). The connectors used in vehicles occupy a considerable space because heavy protection is required against transmission interruption caused by vibration. In addition, a significant number of wires are used together in a junction box to increase total wire length (e.g. 55L when 10 ECUs are connected) and thus weight increases accordingly. © 2014 IEEE.

A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links.

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. © 2014 IEEE.