論文

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%-10.2% over a load resistance range of 0.1-2 k$\Omega$. © 1966-2012 IEEE.

This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves 6Gb/s data rate and almost 10% power transfer efficiency over a 100-2kΩ range of the load. © 2010 IEEE.

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

In this work, we measured 1=f noise of independent-double-gate-(IDG-) fin-type FET (FinFET) which has two independent gates. Flicker noise of common-double-gate-(CDG-) mode which both gates are applied with the same voltage and IDG-mode that has one gate voltage grounded and the other gate voltage applied with arbitrary voltage, and both result were compared with the same drain current (Id). First, we measured relationship between characteristic of the normalized 1=f noise by Id (SId =I2 d ) and characteristic of Id. Both the SId =I2 d of IDG-and CDG-modes show nearly equal values and tendency. Next, this work also shows the relationship between 1=f noise and vertical electric field (Ei) of surface of gate oxide film. As a result we could not definitely see a large margin of 1=f noise between CDG-and IDG-modes from Ei. This work also discovered that 1=f noise was greatly influenced by Id density. © 2013 The Japan Society of Applied Physics.

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm. © 2012 IEEE.

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step. © 2011 JSAP (Japan Society of Applied Physi.

A 100Mb/s 1.37mW impulse-radio ultra-wideband (IR-UWB) receiver with Costas-loop based frequency and phase synchronization scheme is developed in 65nm CMOS. This is the first analog-domain plesiochronous solution for IR-UWB communication in DC-960MHz band without the necessity of traditional analog-to-digital converter (ADC) and digital baseband for signal processing, thereby the receiver achieves the lowest energy of 13.7pJ/bit in state-of-the-art plesiochronous IR-UWB communication. © 2012 IEEE.

This paper presents a high data rate, non-contact interface using a coupled transmission line (CTL) composed of two differential transmission lines. The proposed CTL can achieve a measured loss of-13.4 dB and a 3-db bandwidth of 3.4-9.0 GHz as a non-contact channel for a 1-mm communication distance. This wideband characteristic makes it possible to achieve high-speed communication using a single channel. The hysteresis buffer-based receiver recovers the transmitted data from the distorted waveforms derived from the AC coupling characteristics of the channel. The interference from the power delivery coil to the CTL is also evaluated. The simulated results showed that the interference was less than-57.8 dB at 13.56 MHz. The system could achieve a communication speed of 12 Gb/s with a BER < 10-12 at a communication distance of 1 mm both with and without a wireless power supply of 75 mArms. The timing margin with the wireless power supply was 41 ps (=0.49 UI). © 1966-2012 IEEE.

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed, which is the world's fastest data link speed with multi-drop bus architecture. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI). © 2013 IEEE.

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed. The transmission line has 5-convex portions to form one side of a coupler where the transmission line width is adjusted to control the characteristic impedance of the coupling section, minimizing signal reflection from each section. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI) where the test chip transmitter occupies 3,750 μm2 and the receiver occupies 750 μm2 with 90nm CMOS technology, consuming 40mA and 23mA respectively at the supply voltage of 1.2V. © 2012 IEEE.

The expanding capacity of today's memory cards and increasing speed of processors have created demands for high data rate interfaces between memory cards and processors. Compared to conventional contact pins, wireless interfaces have received tremendous interest for reasons of more convenience, higher reliability, and higher data rate. Two major types of near-field wireless communication techniques using capacitive coupling and inductive coupling channels have been investigated. Tens of Gb/s/ch is achieved using both methods with a communication distance of tens of microns in TCI (thru-chip-interface) applications [1-2]. However, when the communication distance denters the mm range in such applications as non-contact memory cards, the sizes of capacitors or inductors must be up scaled to detect enough electrical flux or magnetic flux, whose magnitude decay as 1/dn (n>1). As a result, the self-resonance frequency fSR is reduced significantly, which becomes the dominant limiting factor for the achievable data rate, since the maximum data rate is usually chosen as 1/2 or 1/3 of fSR in order to avoid signal peaking [3]. Although multi-channel solutions are viable to increase the total data rate, complex systems are required to address the skew issues in synchronization, and low area efficiency is resulted to reduce crosstalk interferences as shown in Fig. 28.3.1. © 2011 IEEE.

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

© 2019 IEEE In this paper, a noble gas sensing system using a large scale integrated resistive sensor array and its interface system is introduced. Accuracy improvement, compared to conventional techniques, was achieved using our proposed opamp output impedance calibration technique. This technique makes it possible to use a low power, weak drivability opamp in the interface circuit. This paper shows the calibration method which reduces the sneak path current error from 83.6% to 1.2% through MATLAB simulations. A prototype system with 1,024 gas sensors integrated in one chip, discrete ICs of opamp, ADCs, and an FPGA was developed, and the effectiveness of the system is demonstrated.

© 2019 JSAP. Ppm-level hydrogen and ammonia in air were recognized by low-power, integrated sensors consisting of catalytic metal nanosheets. Thermal energy necessary for catalytic reactions were given by Joule heating not by external heaters. The thermal-aware design of sensors reduces the power consumption to 0.14 mW. The low-power and small-area properties enable large-scale, on-chip integration of molecular sensors, which will be useful in IoT era. A sensor array was successfully connected to a platform with wireless connectivity.

© 2019 The Japan Society of Applied Physics. Ppm-level hydrogen and ammonia in air were recognized by low-power, integrated sensors consisting of catalytic metal nanosheets. Thermal energy necessary for catalytic reactions were given by Joule heating not by external heaters. The ther-mal-aware design of sensors reduces the power consumption to 0.14 mW. The low-power and small-area properties enable large-scale, on-chip integration of molecular sensors, which will be useful in IoT era. A sensor array was successfully connected to a platform with wireless connectivity.

© 1963-2012 IEEE. H2 and NH3 detection with low power consumption was demonstrated by integrated chemiresistive Pt and PtRh nanosheet sensors on glass substrates. The self-heating effects realized low power and local heating of metal nanosheet sensors, enabling the integration of sensors with different operating temperatures. Based on different resistance changes in Pt and PtRh nanosheets toward H2 and NH3, the concentration of each gas was detected from a gas mixture by consuming around 1-mW power. For decreasing the power consumption and further integration of sensors, sensor scaling and pulsed operations were numerically and experimentally studied. In addition to good connectivity of metal nanosheet sensors to large-scale integration (LSI) circuits, improvements of the power consumption by sensor scaling were proven. The pulsed operations required for integrated sensor arrays maintained a sensor response, or a resistance change, of approximately 60%, even when the power consumption was reduced by 20%.

© 2018 IEEE. Time reduction technique for the measurement of input referred noise of dynamic comparator is presented. By using binary search technique, the proposed method can reduce the measurement time of comparator input referred noise to (log2n)/n, where n is a required resolution. Experimental results obtained by the developed measurement system shows good correspondence with the simulated input referred noise.

© 2017 IEEE. In this paper, a complete wireless power transfer system with transmitter (TX) and receiver (RX) chips is presented. Both RX local and TX wireless output voltage regulations are achieved by the proposed constant-idle-time control without using any wires or additional discrete components, such as MCU, DAC, various kinds of controllers, and decoders, which were required in previous works. The system and circuitry design complexity is significantly reduced. Both TX and RX chips are fabricated in the TSMC 65-nm process with standard 2.5-V I/O devices, and the RX coil is fabricated using flexible printed circuits to demonstrate the performance for implantable applications. Up to 17.5% end-to-end total efficiency improvement is observed when enabling the wireless constant-idle-time controlled TX voltage regulation, and an instant load-transient response is also achieved. As a result, compared to previous works, this design achieves a higher total efficiency, a faster load-transient response, and a higher level of integration with a much lower system and circuitry design complexity.

© 2019 IEEE. This work presents a novel idea to dynamically control a differential ring oscillators biasing in order to improve the phase noise performance in the ultra low power domain. This proposed feedback system can be flexibly applied on any type of fully-differential ring oscillator with a tail current source. The following paper covers theoretical and simulative considerations to prove the feasibility of this idea. Finally measurements of a 180 nm standard CMOS integrated prototype system depict the implementability of this idea. A phase noise improvement of up to 35 dBc/Hz can be observed with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by 434% in contrast to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz.