論文

This paper proposes a disjoint path selection scheme for generalized multiprotocol label switching (GMPLS) networks with shared risk link group (SRLG) constraints. It is called the weighted-SRLG (WSRLG) scheme. It treats the number of SRLG members related to a link as part of the link cost when the k-shortest path algorithm is executed. In WSRLG, a link that has many SRLG members is rarely selected as the shortest path. Simulation results show that WSRLG finds more disjoint paths than the conventional k-shortest path algorithm. In addition, since WSRLG searches for the weight of the SRLG factor by using a binary search algorithm while satisfying the required number of disjoint paths between source and destination nodes so that the cost of a path set can be minimized, it can find the most cost-effective disjoint paths. © 2002 IEICE.

This paper proposes the hierarchical cloud-router network (HCRN) to overcome the scalability limit in a multi-layer generalized multi-protocol label switching (GMPLS) network. We define a group of nodes as a virtual node, called the cloud-router (CR). A CR consists of several nodes or lower-level CRs. A CR is modeled as a multiple switching capability (SC) node when it includes more than one kind of SC, which is fiber SC, lambda SC, time-division multiplexing (TDM) SC, packet SC, even if there are no actual multiple switching capability nodes in the CR. The CR advertises its abstracted CR internal structure, which is abstracted link state information inside the CR. A large-scale, multi-layer network can then achieve scalability by advertising the CR internal structure throughout the whole network. In this scheme, the ends of a link connecting two CRs are defined as interfaces of the CRs. We adopt the CR internal cost scheme between CR interfaces to abstract the network. This CR internal cost is advertised outside the CR via the interfaces. Our performance evaluation has shown that HCRN can handle a larger number of nodes than a normal GMPLS network. It can also bear more frequent network topology changes than a normal GMPLS network. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

This paper describes network resource management techniques which are the key to exploiting the benefits of VP-based ATM networks. In ATM networks, the Virtual Path (VP) concept has been established which enables separation of the logical path capability from the physical interface structure. This is an inherent benefit of VPs and will greatly enhance network flexibility and performance. However, the benefits of ATM can only be utilized through a new network resource management technique and a Usage Parameter Control technique, which are described in this paper.

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The N × N matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N-2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and output ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at 'm' times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing, both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

This paper proposes an ATM traffic management method that utilizes a deterministic source traffic descriptor, a deterministic Usage Parameter Control (UPC) algorithm and a conservative statistical bandwidth allocation method all of which were developed considering the Cell Delay Variation (CDV) typically experienced in ATM networks. For the source traffic descriptor, sliding time interval-type descriptors are proposed. A newly-structured UPC method which combines a sliding window-type circuit and a 2-phase credit window type circuit is proposed. The method is precise and accurate and requires only a small amount of hardware. The proposed parameter conversion method considers the CDV generated between User and UPC point. A bandwidth allocation method based on the worst clumping pattern and UPC output pattern is proposed. The network efficiency degradation caused by CDV is calculated. This traffic management method not only guarantees the QOS of all connections but also allows for large statistical multiplexing gains. The proposed method will, therefore, make it possible to create a more effective B-ISDN, one that can offer cost-effective broadband VBR services.

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8-Gb/s optical-input/optical-output four-channel time-division switch, a 1.8-Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0-Gb/s electrical-output 4:1 multiplexer, and a 2.8-Gb/s electrical-input/electrical-output 4 × 4 space-division switch. It uses a new multistage 2 × 2 switch block with small hardware and high-speed operation. It can be expanded to a 16 × 16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN.

The authors present the main points of a recently developed experimental ATM (asynchronous transfer mode) transport system and the key virtual path (VP) management techniques. The ATM network configuration and the developed ATM cross-connect and add/drop multiplexing (ADM) systems are outlined. They describe the design considerations of the VP management techniques, which include VP bandwidth specifying parameters. The newly developed usage parameter control techniques are then presented. An analytical method for evaluating cell multiplexing delay and cell loss characteristics for multimedia signal sources is developed. Next, by utilizing this method, a link capacity-design algorithm for accommodating VPs is proposed. Finally, the performance and application areas of the proposed algorithm are evaluated.

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GaAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit.

A high-speed 8 × 8 space-division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B-ISDN. The LSI employs a new circuit design and super self-aligned process technology (SST-1A), and is switched successfully with a bit error rate of less than 10-9 at 2.5 Gbit/s using a 29-1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL-compatible interface, -4.0 V and -2.0 V power supply voltages, and power dissipation of less than 997 mW. High-speed address control memories (ACMs) are integrated monolithically into the LSI, which can operate both synchronously and asynchronously.

A high-speed multichip 32 × 32 space-division switching module for high-definition TV broadcasting and switching systems is described. This module employs a novel Si-bipolar SST (super self-aligned process technology) switching LSI and a multilayer substrate with a polyimide dielectric and a fine pattern of copper conductors. The substrate contains matrix-shaped thin-film resistors for terminated transmission and has a spiral via hole structure to increase fabrication reliability. The module has 50-Ω characteristic impedance transmission lines that have a small deviation of less than 2.5%. The multichip module can handle a signal speed of 1.8 Gb/s using 1:1 and 1:n connections. Performance results confirm that this module will be suitable for future B-ISDN (broadband integrated services digital network) communication systems.

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16 × 16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated.

An 8 × 8 and an expandable 16 × 16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29 - 1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 × 8 LSI and 2.8 W for the expandable 16 × 16 LSI.

An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems ot future B-ISDN.

An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW.