論文

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

This paper proposes a new adaptive remote rate control based on extrapolation called AREX. AREX does not require a high-speed switching node to have high calculation load. Consequently, transit switches with high-speed interface do not always need to have high calculation power. As a result rate control can be implemented easily in a WAN. AREX reduces the major problems of feedback rate control, inaccuracy of feedback information and large necessary buffer space caused by long propagation delay. In AREX, a high-speed transit switching node only observes the link utilization ratio of the output VP and notifies it to upstream nodes. Local switching nodes with spare calculation power calculate and control the output rate of each VC. Because the admissible cell rate of each VC is calculated by local switches, ABR service can be emulated there. This paper describes the mechanisms of AREX and discusses the function form that determines its characteristics. AREX tries to converge utilization to the target value. The relationship between target value and overload probability is clarified for network management. The performance of ABR emulated by AREX is evaluated by computer simulation. The results show that AREX provides high throughput and requires less buffer capacity even in a network with long propagation delay.

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput.

We have developed compact 10-Gb/s optical transceiver and receiver modules for a WDM sub-Tb/s ATM switch system. Each module has a cooling part whose structure is based on a high-performance heat transfer device and micro-fans. Instead of a conventional radiation fin, a high-performance device is used to conduct heat from heat sources, such as a laser, to the fin inside the duct on the end of the module, where it is radiated by push-pull micro-fans. Because the conventional cooling structure based on straight fin occupies a larger volume, it is not suitable for high-density arrangement. Our cooling system achieved a heat resistance value of 1.8 °C/W, which was sufficient to stabilize the operation of the laser unit. This cooling structure enables a compact structure to handle high-density heat generation. The power dissipations of the TX and RX are 9.65 and 22.5 W, respectively. The TX and RX modules are the same size: 80×120×20 mm. Measurements show that these optical modules can operate stably without any additional cooling systems even in the switching unit.

This paper proposes new scheduling mechanisms for meeting fairness criteria which are not met by conventional scheduling mechanisms such as WRR. These proposed mechanisms utilize the arrival of untagged cells at an ATM switch not only for frame drop policy but also for deciding which VC cell is eligible to be serviced. GFR service using the proposed mechanisms can provide the users with bandwidth allocation which meets several fairness criteria.

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The flrst step system was to use advanced Si-Bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm Bipolar SST technologies and Cu-Polyimide multilayer MCM realized a 160 Gb/s through-put ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper flrst reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8 × 8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems.

We propose a lightweight measurement-based admission control method. The instantaneous rate estimated with a low-pass filter (LPF) and the maximum instantaneous rate (MIR) observed during the monitoring period is used to determine the residual bandwidth. Hence, we call this the MIR method. We demonstrate the use of the LPF design method to obtain the instantaneous rate accurately. We develop an analytical model and investigate the performance of the MIR method. We compare the MIR method to a conventional measurement-based admission control method with respect to bandwidth efficiency and implementation complexity. We demonstrate that the MIR method can be implemented with a simple circuit while achieving a bandwidth efficiency that is comparable to the conventional method. © 1998 Scripta Technica.

The authors have developed a very compact set of 10Gbit/s optical transceiver and receiver modules, each 80 × 120 × 20mm3. A novel cooling structure based on a high-performance heat-transfer device and micro-fans, achieving a heat resistance value of 1.8°C/W, enables the high-density heat generation to be handled in such a small module.

This paper proposes a new network architecture, ALPEN (ATM multi-protocol emulation network), based on a new concept for realizing full-scale multimedia communication networks. In ALPEN, various communication protocols, such as ABR (available bit rate), FRM (fast resource management), or SHM (short hold mode), can be handled using a single, simple transit network. Each protocol is emulated at the edge node of the WAN (wide area network), and the status of the transit network is checked by periodically examining the residual bandwidth information of each route. ALPEN is a cost-effective and flexible network architecture because it enables us to implement new services or protocols easily by modifying only the edge nodes. In ALPEN, since individual edge nodes periodically obtain the bandwidth information, it is possible to respond promptly to a user's request to change his bandwidth. In particular, when the network's RTT (round trip time) is long, as in a WAN, ALPEN is a promising way to resolve the problem of performance responsibility. Although each edge node periodically checks the disperse information to all destination edge nodes on a residual bandwidth, the information might be old, or it might be necessary to process it independently at the multiple edge nodes. There-fore, the parameter of "effective residual bandwidth" is estimated by a statistical method; the estimation also considers that bandwidth resources may be overbooked by multiple edge nodes. The statistical method is described in this paper. The ALPEN introduced in this paper is an effective architecture that makes it possible to implement new or various unforeseeable network services in the future multimedia era, in which various services and protocols may exist simultaneously. © 1998 Scripta Technica.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4Gbit/s with a large level margin can be attained.

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture, and will be suitable for future high-speed multimedia ATM networks.

When a multicast cell at an aynchronous transfer mode (ATM) switch requires distribution of its copies to the multiple users and/or outgoing sub-rate links served by one of its output ports, multiple cell copies at that output port are required. The conventional copy approach and broadcast approach of multicasting either cannot handle such situations or handles at the cost of switch performance. In this letter we propose a technique to enhance the ability of the copy and broadcast approaches to multicasting to enable them to handle such situations efficiently and economically.

This paper proposes a high-speed input and output buffering ATM switch, named the Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

This paper describes newly developed advanced ATM switching system hardware structures. They are based on the Si-Substrate MCM-D technology which integrates ASIC custom VLSIs, high-speed S-RAMs and FPGAs (Field Programmable Gate Arrays). The MCM-D module realizes the ATM layer function by combining a high-performance ASIC with high-speed S-RAM cache. This is made possible by high density packaging and high-speed (20 ns) access to 1-Mbit of memory. The MCM employs 8 S-RAMs, possible with the stacked RAM technique, to reduce module size. This sub-module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

We have developed an ATM switch ceramic multichip module (MCM) that has an aluminum substrate. This MCM can support a high-density mounting and high-speed interconnection among LSI chips. Using LSI technology, ceramic-substrate technology, high-speed/high-power connector technology, and compact liquid-cooling technology, we built an 80-Gbit/s ATM switching module.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

This paper proposes a new scheduling algorithm for input-queued ATM switch, called iterative quasi-oldest-cell-first (i-QOCF) algorithm. In i-QOCF, each input port and each output port maintains its own list. The length of the list can be N, 2×N, ..., B×N, where B is the size of the buffer that queues cells destined for an output port. The list maintained by an input port contains the identifiers of those output ports to which that input port will send a cell. The list maintained by an output port contains the identifiers of input ports which have a cell destined for that output port. We show the performance of i-QOCF and results in which we compare i-QOCF with i-OCF in terms of cell delay time. We find that an input-queued ATM switch with i-QOCF and virtual output queue (VOQ) can achieve 100% throughput for independent arrival processes. The 3-QOCF is enough to achieve convergence during one cell time. If we use a 3-QOCF in which the list length is 3×N, then its cell delay time performance is almost the same as that of a 4-OCF.

A multi-stage switching architecture is a key technology for budding a high-speed ATM switching system. An effective way to make a multi-stage switch nonblocking is to use cell-based routing. However, cell-based routing may cause cell-sequence disorder at the output of the switching fabric. This paper proposes a hierarchical cell-sorting (HCS) switch architecture, which is a nonblocking multi-stage AIM switch using cell-based routing technology. Each basic HCS switch performs cell sorting at every crosspoint, based on timestamp information in the cell-header. This arranges the cells in sequence at the output of each basic HCS switch, since the crosspoints are hierarchically interconnected from the input port to the output port of a basic HCS switch. A multi-stage HCS switch is constructed by interconnecting the input and output lines of these basic HCS switches in a hierarchical manner. Thus, the cell sequence in each final output of the multi-stage switch is preserved in a hierarchical manner. In this way, cell-based routing with 100% throughput is achieved, with no need for internal speed-up techniques.

This paper proposes a distributed traffic control method for large multi-stage ATM switching systems. In the proposed switching system, each port of the basic switches has its own traffic monitor, and each line unit (LU) periodically obtains congestion information about available paths from OAM cells in order to route a new virtual circuit independently. The performance of the proposed system depends on the interval between OAM cells. We show how an appropriate interval can be determined in order to maximize the number of user cells that each LU can send.