論文

An over 1 Tb/s scalable ATM switching system architecture is proposed suitable for the mature B-ISDN environment. Two kinds of switch modules are combined, the small-scale switch with VC and VP-level management named AHM having 10 to 20 Gb/s throughput, and the high-speed and simple routing switch named AMC offering simple ATM layer management for AHMs-interconnection. AMC resource management employs the Grouped VP resource management scheme only at AHM. The proposed system architecture gives high statistical multiplexing gain from small-size switches to over 1 Tb/s switches and easy management; switching capacity can be efficiently expanded. As the switch architecture of the AMC, a high-speed and scalable ATM switch architecture, named TORUS-switch, is proposed. The switch is an internal speed-up crossbar-type switch with cylindrical configuration. The self-bit-synchronization technique is adopted to achieve high-speed cell transmission without requiring high-density implementation technology. Also, distributed contention-control based on the fixed output-precedence scheme is newly adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultra-high-speed crosspoint LSI using the advanced Si-bipolar process to confirm its feasibility. Measured results confirm that the TORUS-switch can be used to realize a expandable tera-bit-rate ATM switch that is also efficient.

This paper presents a low-power large-capacity ATM switching system design and modules (LSI and MCM). The design uses MCM technology with a copper-polyimide substrate, 150-μm pitch outer lead TAB and 98-highway flexible printed circuit cables for high-density packaging and high-speed operation. Using these technologies, a 160 Gbit/s ATM switching system with a power dissipation of about 1.3 kW can be achieved for future Broadband ISDN systems. This power is 65% of that of the reported system which uses ECL I/Os, and can be cooled by forced air with conventional fin-structures.

This letter presents SAM, a multiplexer for ATM's circuit emulation services that can precisely control the cell clumping at the connection-level. Compared with a FIFO (First In First Out) multiplexer, it also improves the connection-level diffusion and CDV (Cell Delay Variation) performance. SAM can therefore significantly increase the number of connections accepted by CAC (Call Admission Control) procedures in the subsequent multiplexer.

ATM networks have the potential to achieve switch cost reduction and multi-level network availability because of their high flexibility. For that purpose, this article proposes to use Virtual Circuit (VC) route self-healing schemes to achieve a multiple-availability-level ATM network. First, the advantages of VC route restoration for ATM networks are presented; Virtual Path level and physical level restoration strategies are then compared. The concept of Full-Net is explained, and the self-healing scheme of a VC route is proposed. Finally, the impact of the logical network configurations on network survivability and resource management is presented.

The performance limitation of the 'Leaky Bucket algorithm' is analyzed for usage parameter control and traffic management in Asynchronous Transfer Mode (ATM) networks. Simulation results show that the conventional statistical bandwidth allocation method, which uses 'the worst pattern derived from the cell interarrival time moments' permitted by the Leaky Bucket algorithm, can not guarantee the QOS. As a result, this paper proves that the VC/VP bandwidth allocation method based on the Leaky Bucket algorithm is unsatisfactory.

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

A new approximation calculation method, named the Recursive Matrix-calculation (RM) method, is proposed. It uses matrix calculation to determine the number of link disjoint paths under a hop link number constraint, i.e. hop limit. The RM method does not overestimate the number of link disjoint paths. When networks are designed by this method, network reliability is perfectly guaranteed. Moreover, the RM method is based on matrix calculation, so CPU time can be reduced by using super-computers equipped with vector processors. Simulation results confirm that the RM method yields rapid approximations that are conservative. Thus the proposed method is very useful for designing reliable multimedia networks.

A uniquely-structured Usage Parameter Control (UPC) method named Virtual-shaping is proposed which considers cell arrival time jitter between user and UPC point. The method uses a modified Dangerous Bridge UPC circuit (Sliding window type) and virtually (logically) shapes cell traffic using cell arrival time compensation to offset cell delay variation (CDV). In addition, the proposed method is based on a cell-buffer-less structure and can be realized with reasonable hardware. The method yields precise and accurate monitoring. Computer simulations show that the method offers higher network utilization than the conventional Leaky Bucket based UPC method. The proposed method will make it possible to create more effective B-ISDNs, and more cost-effective broadband VBR services.

This paper describes a 320 Gb/s high-speed multichip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCM's that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSI's are mounted on MCM's using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput, which is applicable for future B-ISDN.

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

This paper describes a 320 Gb/s high-speed multi-chip ATM switching system for broadband ISDN. This system employs a Copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCM using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput and it is applicable for future B-ISDN.

This letter proposes a VP-shaper for ATM networks that controls the VC-level cell clumping. The new shaper is compared with a conventional shaper and is found to significantly increase CAC (Call Admission Control) efficiency and achieve high VP utilization gain. Hardware implememation based on a shared buffer and chained lists is presented and its feasibility is shown.

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers: a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless high-speed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.

A T-bit/s ATM switching system architecture, called the OPTIMA switch, is proposed. This system is scalable and quasi-non-blocking by virtue of its self-load-balancing mechanism and high-speed interconnection effect. The self-load-balancing mechanism prevents overloading in the switch by automatically checking and balancing the internal load. An experimental 640-Gbit/s ATM switching system was developed and tested; the basic parts of switching function are demonstrated. The switching system was fabricated using advanced 0.25 mm-CMOS devices, high-density MCM technologies, and optical WDM interconnection technologies. The WDM interconnection system, a key part of the scalable 640-Gbit/s OPTIMA switching system, interconnects 80-Gbit/s switching modules using WDM routing technology. The developed 640-Gbit/s switching system can be applied in the creation of a platform for future high-speed multimedia network.