論文

A high-speed 32 × 32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8 × 8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.

A Si bipolar 2 Gbit/s 16 × 16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology SST-1A. This LSI is applicable to future B-ISDN HDTV switching systems.

The authors propose a novel structure for a high-speed multihighway serial-to-parallel converter for future high-speed digital switching systems. The proposed structure consists of a two-dimensional shift register array that can shift both horizontally and vertically. The shift direction is changed at the frame periods. The calculated results confirmed the superiority of the proposed structures over conventional ones, namely, faster operating speed and fewer gates.

A broadband ISDN architecture is proposed, and its requirements are discussed. The structure and traffic characteristics of a broadband switching system using multirate switching technology are described. A high-speed time-division switch for broadband circuit switching is presented. It uses a high-speed time switch, a serial-to-parallel converter, and peripheral ICs, all of which operate at over 512 Mb/s. Experimental results are presented.

A high-speed time-division switch used in a 32-Mb/s bearer-signal communications system is described. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large-channel-capacity time-division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time-division switches necessary for such services as TV and high-definition TV communications.

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin. Copyright © 1986 by The Institute of Electrical and Electronics Engineers, Inc.

A Si bipolar very high-speed 8-channel multiplied by 8-bit Serial/Parallel and Parallel/Serial conversion LSI (SPPS-LSI), having 1. 5 Gb/s throughput is developed for high-speed digital communication systems. To achieve high performance, a novel data conversion method is adopted. By applying a sophisticated circuit design and SST-1A process technology, a high-speed and low-power LSI is achieved with small chip size.

This paper presents the development of high-speed logic ICs having the same function as the ECL100K family for high-speed digital system applications such as for time division switching systems. A Super-Self-Aligned process Technology (SST) and a low-voltage swing differential circuit technique are used. The ICs operate up to about 2 Gb/s under a chip power dissipation of 170 mw-570 mw.

The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.

This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s multiplied by 64 channels) are obtained.

Precise observation of the single longitudinal mode spectrum for distributed feedback lasers revealed fine structures when the spectrum was broadened by high-speed modulation. A dynamic simulation can explain reasonably the above behavior if the model takes into account the carrier density modulation enhanced by the relaxation oscillation. In this work, experimental results where both modulation depth and speed were varied are described along with a calculated result.

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell not arrival allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

New network survivability measures are developed and compared with conventional ones. The advantages of using multiple survivability measures, including the new ones, are discussed. The measures are illustrated and interpreted through several numerical examples. We also show how survivability can be included as a constraint in network optimization models.

A new adaptive rate control with congestion prediction is developed that is highly robust against long propagation delays. It minimizes the network performance degradation caused by the delay based on prediction by extrapolating past data and correction using new notification. The simulation results show that our proposed control maintains high throughput and a smaller buffer even in long propagation delay networks, like ATM-WAN.

This paper proposes a rate control technique for high-speed burst transmission with quick response in ALPEN, an ATM Multi-protocol Emulation Network. Under lower load, it is desirable for the network to allow very quick burst access to a lot of bandwidth, like UBR. Under higher load, a mechanism for congestion avoidance or recovery is required, like ABR. The rate control technique proposed in this paper provides both properties. In ALPEN, the transit switch sends only information about the residual bandwidth to the source side edge switch. The edge switch responds to user requests quickly because it knows route status. This is very effective because long delay in ATM-WAN reduces response performance. The proposed technique improves ATM-WAN performance because it has a algorithm to collect the information about route status without using any knowledge about delay length. Its performance is confirmed by simulations.

A 640 Gb/s ultra-high speed optical switch interconnection system based on Wavelength Division Multiplexing (WDM) is proposed as a Tbit/s ATM switch interconnection system for future B-ISDN. Proposed optical interconnection system uses WDM in switch interconnection to avoid interconnection limitation. The system consists of 8 wavelengths (each carrying a 10 Gb/s signal), eight optical Transmitter modules (Tx), and an 8×8 Arrayed Wave Guide (AWG) optical router which interconnects the 8×8 80 Gb/s WDM signal and 8 wavelengths Receiver modules (Rx). Using a highly statistical WDM optical link, proposed system can attain nearly non-blocking ATM switch interconnection. There are several advantages to the proposed optical interconnection system. First, by adopting a arrayed waveguide filter with wide channel spacing (525 GHz), the system has the wide temperature margin of 10 degree. Second, by setting a Clock Data Recovery circuit in each Rx module, each 10 Gb/s highway interconnect unit switch can function independently. As a result, the proposed system is highly scalable. We fabricate an optical interconnection prototype system and succeed in demonstrating 640 Gb/s optical interconnection. The proposed optical interconnection system can be applied to realize future broadband ATM networks.

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable -Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration that is enable the switch to have scalability. The SDA switch has a crosspoint buffer and transit buffer at every crosspoint. The arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer by way of several transit buffers, then to the output port. Since the arbitration is executed distributedly at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch is able to be expandable and have large throughput. Numerical results show that the SDA switch keeps fairness on delay time. In addition. the maximum delay time and the required crosspoint buffer size in the SDA switch was reduced, compared with that in the conventional switch based on the ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme is a simple and expandable architecture, and it will be suitable for the future high-speed multimedia ATM networks.

A Tb/s throughput ATM switching Architecture, OPTIMA, is proposed for a quasi-non-blocking large switch. The switch uses hardware self-rearrangement with a three stage network, that is traffic control is automatically performed by hardware. The switch thus acts as a non-blocking switch. In addition, optical wavelength routing is used to avoid interconnection limitations. An 8×8 interconnection is realized that uses 8 wavelengths to transfer 10 Gb/s signals. A 640 Gb/s OPTIMA prototype is described. The proposed OPTIMA architecture and 640 Gb/s system can be applied to realize future broadband ATM networks.

This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

As an architecture for a large-scale tera bit/s class ATM switch system, a building-block structure combining multiple small-scale switches (AHM: ATM circuit handling module) and interconnection switches (AMC: ATM intermodule connector) is proposed in this paper. In this proposed structure, mesh-like VP connections are made between AHMs by AMCs. Resource management is not done inside the AMC, but is simply executed inside AHMs which interconnect the AMCs. Resources are managed by the total capacity of connectivity (GVP: grouped virtual path) between the AHM and the input/output side AHM. It is shown theoretically that, with this proposed structure, it is possible to increase effectively the switching capacity in proportion to the number of AHMs connected. A new switch architecture with 160 Gb/s switch throughput is also proposed for application to the large-scale ATM switch system proposed in this paper. The proposed switch is an internal speed-up crossbar ATM switch which is suitable for switching high-speed cells. In order to avoid loss of QoS (Quality Of Service) of cells switched by AMC, it accommodates cells which are accelerated up to 10 Gb/s at the output port of the input side AHM. A new high-speed arbitration control algorithm which is distributed to each output line is adopted in this structure. The proposed control algorithm, in which a logical ring is composed of three buses, has a capability twice that of a conventional ring arbiter can realize very high switching throughput above 160 Gb/s. It is shown that a prototype ATM switch has been developed successfully using a combination of new technologies such as a new switch architecture, high-speed Si-bipolar LSI, and a sophisticated multi-chip module technology, and its functions and performance were satisfactorily confirmed. © 1997 Scripta Technica, Inc.