論文

This article proposes an on-chip photovoltaic cell equipped with a tunnel oxide passivated contact (TOPCon) exhibiting selective carrier contact. The proposed structure utilizes the gate region as the TOPCon structure and performs best when the gate oxide is high- $\kappa$ hafnium oxide (HfO $_\text{2}$ ). Oxide thicknesses lower than 1.5 nm enable the utilization of the device as a solar cell; therefore, it can be fabricated using high-end oriented CMOS processes. Furthermore, TOPCon technology at the bulk contact is observed to be more important than that at the emitter contact; however, a combination of the two yields an improved $\textit{V}_{\text{OC}}$ value. On applying the full TOPCon technology, $\textit{V}_{\text{OC}}$ is improved by approximately 20 mV from 601 to 619 mV, and $\eta$ is improved by approximately 0.5 $\%$ from 15.20 $\%$ to 15.73 $\%$ compared to the conventional surface diffusion (SD)-based structure.

This study presents the design of a novel on-chip photovoltaic device structure. The aim of this study is to avoid shading loss using a double ring structure. The proposed structure forms all contacts under shaded area; therefore, it is free from optical losses due to electrode shading. In addition, this design enhances integration by utilizing the photovoltaic cell space under the shading metals. This space can be used for interconnections or capacitors. The results indicate that the proposed structure significantly improves cell performance by avoiding light shading loss with the shaded contacts. It was observed that the cell efficiency improved by approximately $0.5\%_{\textit {ab}{s}}$ when compared with the conventional structure, indicating that this is the best performance among several on-chip photovoltaic cell devices.

This letter proposes an illumination detection method that employs the output voltage of an on-chip photovoltaic cell. Currently, photo-diode-based optical sensing is significant; however, the use of an open-circuited photovoltaic cell reduces the measurement setup component with the stabilized output at an order of hundreds of mV. This detection system comprises a photovoltaic cell and a comparator. The open-circuit voltage (VOC) of the photovoltaic cell is compared to the reference voltage. These components are fully integrated with 0.18 μm standard complementary metal-oxide semiconductor (CMOS) processed large-scale-integration (LSI) chips. The numerical simulation demonstrates that VOC stabilizes under sufficient bulk quality and depends on the illumination conditions. A reference voltage of 550 mV is set in our results to determine whether the chip was under sunlight or room light, and the experimental measurements of VOC demonstrate well-matched results and the feasibility of our proposed method.

This study reviews the current methods of numerical simulations for crystalline-Si (c-Si) photovoltaic (PV) cells. The increased demand for PV devices has led to significant improvements in the performance of solar cell devices. The main contribution comes from c-Si solar cells, which constitute 90% of the industry. Numerical analysis is effective for predicting, developing, and optimizing cell performances as the cell structures become more complex and include several parameters. However, conventional methods cannot simulate improved device structures with complex configurations. Additional physics is necessary to evaluate these cell structures. This study introduces methods for evaluating these cell structures using physical modeling and highlights the latest examples of simulations of c-Si solar cells.

The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

We assessed the performance of transparent conductive oxide (TCO) materials for use in the heterojunction back contact + (HBC+) solar cell. In addition to indium tin oxide (ITO), titanium dioxide (TiO₂) and zinc oxide (ZnO) were evaluated as possible materials for the rear side of HBC+ solar cells. The results showed that the different optical and electrical parameters of the TCO materials affect the cell performance differently. Of the TCO materials that were assessed, the HBC+ cell with TiO₂ delivered the best performance by increasing the power density by approximately 0.5 mW/cm² (relative to our previous evaluation) under bifacial illumination conditions. The optical properties of the TCO materials were revealed to have the greatest effect on the cell performance, particularly on the rear-side performance. The optimal size of the rear metal area is affected by the properties of the TCO material, mainly by the resistive components, and an increase in the temperature does not affect the selection of the best TCO material.

In this study, a color detection phenomenon that does not utilize color filters is evaluated via the standard CMOS process. The device comprises multiple pn-junctions stacked in the depth direction, which enable division of the light responses by different light absorptions with respect to wavelength. To eliminate the color filters, we use rectifiers to cut the reverse currents corresponding to the long-wavelength infrared (Ir) regions. Numerical simulations predict the dynamic range of the sensor as 160 dB after removal of the filters that can decrease this value. Applications based on the Internet of Things can be realized via mass production at low cost by eliminating the additional processes required to form the conventional color filters in front of the sensor. We evaluate the proposed device by both numerical simulation and experiment as well as clarify that the sensing phenomenon requires sufficient PWell thickness to separate the depletion regions for successful operation. The appropriate process parameters for the CMOS process are revealed, providing useful information for testing under a wide range of process conditions.

This study examined the temperature-related piezoresistance issues of p-type doped 3C-silicon carbide (3C-SiC) materials. Previously, we proposed piezoresistance temperature models that describe phenomena based on the ionization energies of materials oriented for high-temperature operations. This study aimed to determine the ionization energy as a function of the aluminum doping concentration of 3C-SiC. However, at the low-temperature region a drastic decrease in the piezoresistive coefficient was observed, and it was predicted to occur when materials possessing large impurity ionization energy are used under negative thermal strained conditions. This phenomenon is in contrast to the conventional piezoresistance factor $P(N,T)$ that is based on narrow band-gap materials such as silicon or germanium; thus, it provides new insights into low-temperature piezoresistance phenomena.

This study proposes a new ultraviolet-infrared (UV-Ir) compatible sensor fabricated using the standard CMOS process. The concept is verified through a numerical simulation, wherein the standard CMOS process parameters used are evaluated. The proposed sensor is an extension of a previously proposed RGB sensor designed on the standard CMOS process, and calculating the current ratio enables the detection of UV with high sensitivity. In addition, the use of current rectification eliminates the short to middle wavelength region and leaves only the Ir region which is used for detection. High dynamic ranges of 160 dB are ensured for all UV, Ir and RGB which they are excellent for color sensing. Consequently, combined with the previously proposed RGB sensing, the new RGB+UV+Ir sensor is realized without any filters.

We have been proposed on-chip power supply system for a micro system. This power supply system operates application circuit, to achieve a stand-alone chip, referred to as a micro system. In this work, we fabricate the chip to evaluate the on-chip boost power supply that consists of photovoltaic device, ring oscillator and DC-DC boost converter on the same die. The solar cell using N-well and P-substrate outputs about 500 mV and several μW under about 7600 lx lighting. This solar cell generates negative voltage to the P-substrate but the photoelectric conversion efficiency is much higher than the solar cell generates positive voltage. In this work, the integration method is shown to realize the solar cell with negative voltage output and bootstrap charge pump(BSCP) DC-DC converter using triple well technology. The performance of newly designed BSCP DC-DC converter using MIM capacitor and previously designed BSCP DC-DC converter using MOS capacitor are compared. The converter using MIM capacitor shows the much higher voltage conversion ratio than the converter using MOS capacitor. However, designed on-chip power supply system shows a large variation of the output voltage. We discuss the variation and mismatch with simulation considering parasitic capacitances using corner simulation.

© 2019 The Institute of Electrical Engineers of Japan. In recent years, IoT (Internet of Things), which various "things" are connected via the Internet, attracts attention. IoT supports the automation and convenience of various activities by connecting our daily lives. Sensor networks for acquiring information by a huge number of sensor nodes therein is essential for IoT. So, challenges for the realization of this system is the size of the cost and the device. One solution to this problem is the realization of microsystem. In this paper, several methods for improving the performance of on-chip solar cells for microsystem by standard CMOS process are introduced. These are a comb-shape electrode for reducing resistances in semiconductor, reduction of the number of contacts to reduce losses at the substrate/electrode interface and diffusion layers around electrodes for suppressing the recombination velocity at electrodes. These designs improved about 40-78% compared to conventional solar cell design.

© 2020 The Japan Society of Applied Physics. Tunnel Oxide Passivated Contact (TOPCon) is a c-Si solar cell structure with tunneling oxide near the rear electrode. A full-area tunneling oxide provides sufficient passivation and low internal resistance with 1D carrier transport. Carrier tunneling mechanism is the key factor of a TOPCon solar cell; the thicker the tunneling oxide, the better is its ability to prevent minority-carrier tunneling. However, excessively thick oxide degrades majority-carrier tunneling. Therefore, the relationship between tunneling oxide thickness and cell performance is important. In this study, TOPCon solar cell structures are evaluated by varying their tunneling oxide thickness and bulk properties for both p-type and n-type bulk using numerical simulation. It is observed that the difference in bulk type is crucial to TOPCon solar cell performance: n-type material shows better performance because of its smaller minority-carrier tunneling current density and wider range of effective tunneling oxide thickness compared to p-type.

© 2020 Author(s). The piezoresistive effect is characterized by the change in the resistivity of a material relative to mechanical forces exerted on it. Such materials can be used as pressure sensors and are among the most important components for micro-electro mechanical system applications. To date, most research on the piezoresistive effect has been directed toward cubic crystalline materials such as Si; however, the prospective non-cubic materials, such as SiC, are known to have exciting and promising properties. SiC exhibits high-temperature robustness and is chemically stable. It is expected that these properties can be applied to a variety of applications. These materials fall in the category of hexagonal crystalline systems, and it is difficult to evaluate the piezoresistive properties of such materials. In this study, we discuss the piezoresistive mobility model that corresponds to both the cubic and the hexagonal crystalline systems. This mobility model is derived from the empirical fitting of the Gauge Factor (G F) values using the longitudinal and the transverse piezoresistive coefficients and the material-unique fitting parameters. Our proposed method has been implemented in the original device simulator and has been evaluated with respect to both Si and SiC materials. This report shows the well-matched G F values and suggests that the proposed piezoresistive effect model can be implemented in device simulation modeling.

We report on the evaluation of cell performances of the bifacial passivated emitter and rear cell (PERC) structures for both p- and n-type Cz-Si. We compared four conditions: Front-side illumination, with and without the rear metal contact, rear-side illumination, and double-side illumination. Furthermore, the effects of the rear contact area and the rear passivation surface recombination velocity (SRV) were evaluated. The numerical simulations were based on the experimental results of the p-type bifacial PERC performance, and we attempted to determine optimized cell designs for each condition. The results showed that the rear passivation SRV determined the bulk condition: An n-type bulk resistivity of 1 $\Omega$-cm and p-type bulk resistivity with BO-cluster deactivation of 0.5 $\Omega$-cm were suitable for a smaller and larger SRV, respectively.

The diffusion profiles of the front floating emitter (FFE) and front surface field (FSF) in a bifacial interdigitated back contact solar cell are optimized. The optimization results revealed that the FFE and FSF schemes are beneficial for enhancing the cell performance at the front and rear sides, respectively. Lighter doping is particularly better for the FSF scheme, and the FFE scheme requires a large diffusion depth for improving the performance. Increasing the area of the rear emitter boosts the performance of the cell, and an FFE scheme with 90$\%$ rear emitter area is found to be the best design. Quantum efficiency mapping demonstrated that the FFE scheme suppresses the loss at the back surface field region, thereby enhancing the performance of the total cell. The FSF scheme improves the quantum efficiency for the entire region by enhancing the carrier transport in the vertical direction. Furthermore, loss analysis revealed that the FFE scheme suppresses the recombination loss at the maximum power point, which is an important advantage over the FSF scheme.

We examine the temperature dependence of the piezoresistive coefficients of silicon carbide (SiC) and gallium nitride (GaN) crystals, which are prospective materials for high-temperature applications owing to their wide-bandgap properties. The temperature-dependent piezoresistive coefficients of these materials were obtained by modeling experimental resistance changes using thermomechanical numerical simulations. This work reports the piezoresistive coefficients of 4H-SiC and GaN at the high-temperature environments, which are still not well researched. The results revealed that the temperature dependences of piezoresistive coefficients were strongly related to the ionization energy, and a high ionization energy stabilized the values of the piezoresistive coefficients at high temperatures. Our proposed temperature modeling method helps in predicting the temperature dependence of the piezoresistive coefficient using the value at the room temperature and the ionization energy of the material, which is useful for evaluating the piezoresistive effect at different temperatures during device simulations.

This paper presents a readout for multi-channel neural recording. The proposed architecture is implemented with a system-level frequency-division multiplexing technique and a time-domain delta-sigma modulator. Subthreshold region operation and the time-domain delta-sigma modulator achieves a reduction of the current dissipation. The multiplexing technique in the frequency domain enhances the power efficiency by sharing an instrumentation amplifier and the delta-sigma modulator in each channel. The proposed circuit employs a pulse-width summation technique to achieve frequency-division multiplexing in the time-domain delta-sigma modulator. The multiplexing technique of multiple frequency chopper stabilization can eliminate flicker noise and offsets. The proposed two-channel readout occupies 0.067 mm2 per channel and is designed with 0.18-µm CMOS technology. The spurious-free dynamic range is up to 50 dB in a bandwidth of 625 Hz with a low power consumption of 520 nW per channel.

In this study, we propose an advanced tunnel oxide passivated contact (TOPCon) solar cell structure for bifacial usage. The proposed structure, named advanced industrial TOPCon (Ai-TOPCon), adopts rear-side local carrier-selective contacts to avoid rear-side light-absorption loss. Ai-TOPCon features larger rear-side light currents and improves the power density by approximately 0.28 mW/cm2 for bifacial usage in a 20% albedo scenario. Several types of Ai-TOPCon and industrial TOPCon (i-TOPCon) are evaluated, and the optimization of the structure resulted in a power density of 28.73 mW/cm2. Loss analysis revealed that the reduced Auger recombination volume was the main factor contributing to the improvement of cell performance, and the light-absorption problem was solved by reducing the rear-side heavy-doped region.

A scalable low power consumption high-voltage driver comprising only standard low-voltage CMOS transistors is proposed. The circuit is a Stacked MOSFET high-voltage driver. The proposed design stands out for its low power consumption (in the order of microwatts), small area, scalability and self-sufficiency. The main setbacks to be considered are its low switching speed, in the order of microseconds, and the fact that its applicability is limited to capacitive loads and high resistive loads. This paper reports simulation results obtained through the implementation of multiple designs in 0.18 um CMOS technology.

An on-chip self-powered memory system fully realizable in standard CMOS technology is presented. The memory cells consist of a MOS capacitor operated as an antifuse, which is written by applying high voltage between its terminals during tens of milliseconds. The full system comprises an on-chip solar cell, a cross coupled charge pump DC-DC converter, stacked MOSFET high voltage drivers and CMOS anti-fuse one-time programmable memory cells. The writing of each memory cell can be commanded through a digital signal provided by an on-chip control circuit or other on-chip sensors. The proposed memory system is intended to be integrated in small autonomous on-chip devices. This paper describes each of the components that build up the proposed system and demonstrates its feasibility through results of its implementation in 0.18 um CMOS technology.