Published papers

A new crystalline-Si (c-Si) solar cell design based on bifacial heterojunction back contact (HBC) with a transparent conductive oxide (TCO) is proposed by the numerical simulation method. Three bifacial HBC schemes are evaluated and compared: full-area contact with an increase in the pitch distance, point contact, and point contact with indium tin oxide (ITO). The results reveal that point contact with ITO is the most optimal among the three aforenoted schemes. The bottleneck of bifacial HBC is caused by the extremely low carrier mobility in an amorphous Si (a-Si) region, and this can be resolved by applying ITO to form a full-contact area that covers all surfaces of the a-Si region. A maximum power density of 29 mW/cm2 is obtained from bifacial HBC, which is an extremely high output from a single-junction c-Si solar cell. The improvement in the maximum power density over the monofacial condition is 8% at 20% albedo.

The hole impact ionization coefficient (IIC) of β -Ga2O3 in the 〈 010〉 direction is determined by numerical simulation, as β (E) = 4.0× 105 ċ exp(-3.1 × 106E. The simulation model reproduces the experiment of the Schottky barrier diode (SBD) operation, and the investigation of the IIC is performed by varying the value to obtain the matched breakdown voltage at the reversed bias operation. The breakdown simulation results are consistent with the experimental results, with only small errors. By comparing the input modeling with the electron-only impact ionization, hole impact ionization is dominant for SBD breakdown operations.

The performance of tunnel oxide passivated contact (TOPCon) solar cells is evaluated numerically by changing the tunnel dielectric materials. The conventional SiO2, Si3N4, and Al2O3 and the prospective TiO2 and HfO2 have unique tunnel parameters and fixed charge polarities, both of which affect cell performance. The critical tunnel dielectric thickness is determined by the majority-carrier effective mass, with a lighter majority-carrier effective mass capable of easing the tunnel dielectric thickness control at the wider thickness region. The fixed charge should be considered for the higher bulk lifetime condition, with a maximum cell efficiency impact of approximately 0.5%. By adopting p-type bulk with BO-cluster deactivation and higher resistivity as well as an Al2O3 tunnel dielectric thin film of 1 nm, a cell efficiency of 24.77% is achieved, approximately 0.2% higher than the record efficiency of a large-scale TOPCon that adopts FZ-Si bulk.

β-Ga2O3 has a high potential for power device applications because of a high Baliga's figure and the availability of large-scale wafers. However, the piezoresistive effect of β-Ga2O3 has not been investigated in detail, and its piezoresistive coefficient has not been reported. This study evaluates the piezoresistive coefficient of β-Ga2O3 in the <010> direction using a mechanical stress simulator and a device simulator, which includes our piezoresistive effect model. In this study, the piezoresistive effect model and simulation method are applied to β-Ga2O3 for the first time. The piezoresistor model of β-Ga2O3 is simulated to evaluate the piezoresistive coefficient of β-Ga2O3. The experimentally obtained gauge factor with and without the contact effect is -5.8 and -3.6, respectively. The piezoresistive coefficient with and without the contact effect is -2.0 × 10-11 Pa-1 and -1.2 × 10-11 Pa-1, respectively. The piezoresistive coefficient is used to evaluate the piezoresistive effect at 1000 °C through thermal analysis.

Phoneme identification plays a major role in the field of speech processing. Currently, machine learning-based methods are the mainstream, but for devices that cannot incorporate heavy processing, we proposed a non-machine learning method to detect consonant-vowel positions using consonant classification criteria of voicelessness, Place of articulation, and Manner of articulation. The proposed method is composed of Fourier transform and simple operation and considered to be fully applicable to existing digital signal processors. These methods are implemented in MATLAB/Simulink.

This brief proposes a new crystalline-Si (c-Si) solar cell structure, based on bifacial back-contact and carrier-selective contact solar cell technology. The proposed device, known as back-contact interdigitated carrier selective (BICS), offers the advantage of using existing c-Si solar cell structures. The bifaciality provided by the passivated emitter and rear cell (PERC), back-contact provided by interdigitated back contact (IBC), and carrier-selective contact provided by tunnel oxide passivated contact (TOPCon) are featured simultaneously. The local and full TOPCons are, respectively, applied to the emitter and back surface field (BSF) region. The proposed device has an output density of over 30 mW/cm2 under standard conditions-room temperature with a 20% albedo condition. A comparison with our previously proposed bifacial solar cell, heterojunction back contact (HBC)+, reveals the advantages of the proposed device. The proposed device is operable under a relatively low temperature under 45 °C, whereas HBC+ is suitable for higher temperatures. Therefore, the choice between the proposed device and HBC+ should be based on the climate of the installation location.

This study evaluated nanometer gate length germanium (Ge) transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors. Nanometer-scale Ge and Si junction-less field-effect transistors (JLFETs) were treated for both NFET and PFET devices under a transient response. Consequently, the electrical and thermal self-consistent simulations revealed that hole carrier transport is more challenging at the channel region for PFET, inhibiting process shrinking. Moreover, the results show that self-heating can reach a dangerous stature, particularly when the channel region is thick. This is because the operation of the nanometer-scale Ge and Si JLFETs depends on the quantum effect, which increases the band-gap energy. The suitable channel design for Ge and Si transistors is almost similar; a heavier doping concentration is favorable for Si transistors. The study concludes that optimizing the channel region to fit the band-gap energy is the most crucial aspect for designing transistors.

Gallium oxide (Ga 2 O 3) attracts considerable technological interest because of its high Baliga's figure-of-merit and high breakdown voltages. As the models for the breakdown behavior of n-doped Ga 2 O 3 that consider soft (barrier lowering) and hard (avalanche effect) breakdowns are still lacking, in this study, we model the breakdown operations in <001> oriented Schottky barrier diodes considering both the soft- and hard-breakdown phenomena. The completion of the impact ionization model of β- Ga 2 O 3 in <001> orientation is proposed by determining the hole impact ionization coefficient, thereby reproducing hard breakdown operations. Moreover, a barrier lowering model is determined for reproducing soft breakdown operations. The outcomes of the proposed modeling investigation are expected to be crucial for predicting the reverse-biased operations of β- Ga 2 O 3 in <001> orientation to facilitate further technological development and applications of Ga 2 O 3.

Piezoresistive pressure sensor designed in the standard CMOS process is proposed. The device features the electrical separation by the pn-junction provided by the standard CMOS process, which it does not need any MEMS processes or the post-processes. The proposed device is composed of vertical multi-pn junctions, and two methods of 3-layer and 4-layer are considered with their advantages and drawbacks. It features high-temperature robustness with silicon material, and integrability to silicon devices. It is designed without any additional processes and therefore enables to compatible to the CMOS devices with low-cost and suitable for mass production that are favorable for IoT (Internet of Things) applications.

We propose fully integrated ON-chip thermoelectric (TE) devices comprising sensors and energy harvesters, and designed using a 0.18-μm standard complementary metal.oxide.semiconductor (CMOS) process. A temperature sensor and thermal energy harvester were designed using a standard CMOS process without any additional micro-electromechanical system or postprocessing. Numerical simulations revealed different optimal unit-cell lengths for the energy harvester and sensor; for utilizing the maximum power PMax and open-circuit voltage (VOC), a harvester and sensor require short and long unit cells, respectively. The thermal energy harvester, with a size of 140 × 140 μm, generated nanowatt-order power, and the temperature sensor, with a size of 100 × 150 μm, generated millivolt-order (VOC). The numerical analysis predicts a 2.5 mV (VOC) as the temperature sensor and 0.8 nW power generation by the TE energy harvester at 50. C thermal input under optimized layout flows. Examples of layout flows are useful to investigate how portable Internet of Things devices work under the everywhere to monitor thermal environments.

This study presents a novel voltage reference topology designed based on a self-generated millivolt reference obtained from multiple on-chip integrated photovoltaic cells. The difference in the open-circuit voltage (VOC ) between two photovoltaic cells (Δ VOC ) is used as the voltage reference. A heavily-doped region is formed at the silicon/contact interface, which functions as the electrical passivation that changes the order of the surface recombination velocity from 106 - 107 cm/s to 102 cm/s. Therefore, we employ one electrically passivated cell and one un-passivated cell in the proposed voltage reference topology. The illuminance-independent Δ VOC, which is temperature dependent, is generated by using the two cells. Therefore, including an additional VOC with the coefficient (α VOC ) successfully eliminates the temperature-dependency and satisfies the voltage-reference demands. We performed a numerical simulation analysis, which demonstrates that an area of <0.001 mm2 is available in the two cells topology, and a total area of 0.0014 mm2 is required to eliminate the temperature variations in the three cells topology.

© 2019 IEEE. This paper presents a delta-sigma modulator with frequency division multiplexing (FDM), which employs analog-domain and digital-domain mixers. The proposed circuit includes chopper stabilization for eliminating flicker noise and is suitable for electroencephalogram (EEG) acquisition front-end. The proposed technique does not require extra digital signal processors for frequency-domain conversion and achieves high area efficiency. We optimize chopping frequencies to minimize crosstalk and analyze dynamic range. The performance is verified by MATLAB/Simulink simulation and measurement of the two-channel prototype fabricated in 0.18 μm CMOS technology.

© 2017 IEEE. We propose an automatic synchronous PLL system for N-path filter for hum noise reduction in EEG(electroencephalogram) measurement by 0.18 μm CMOS process. Monitored common mode waveform contains Hum noise frequency component during EEG measurement is used for a master clock frequency of the N-path filter. The hum noise frequency as a master clock of the PLL is compared with a rectangular wave obtained by dividing the output frequency of the VCO which is aimed to oscillate at 400 or 480 Hz by 8. The oscillation frequency of the VCO is controlled by the bias voltage. The output signal of the VCO is inputted to a logic circuit that generates an 8-bit digital waveform, and the output for controlling the N-path filter is generated. It is possible to attenuate 50 or 60 Hz component of the EEG signal contains hum noise through an N-path (N = 8) filter. We simulated the PLL (PFD-CP, VCO), logic circuit, N-path filter and measured characteristics of the implemented PLL and logic circuit in this research.

© 2017 IEEE. This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.

© 2020 Trans Tech Publications Ltd, Switzerland. A numerical simulation of p-type 4H-Silicon Carbide (4H-SiC) piezoresistance coefficients in (0001) plane evaluation is shown in this study. A 4H-SiC material has outstanding material characteristics of wide band-gap of 3.26 eV and high temperature robustness. However, many material properties of 4H-SiC material are still unknown, including piezoresistance coefficients. Piezoresistive effect is resistivity change when mechanical stress is applied to the material. Piezoresistance coefficients express the magnitude of this effect, important for designing a mechanical stress sensor. In this study, reported piezoresistance coefficients of p-type 4H-SiC in (0001) plane is evaluated based on numerical simulation. The simulated results of Gauge Factor (GF) values (determined by (ΔR/R)/ε (R is the resistance and ε is the strain of material)) well matched to the theoretical GF values (determined by πE (π is the piezoresistance coefficient and E is Young’s modulus of the material)), shows that reported piezoresistance coefficients are reliable. Also, the internal mappings of piezoresistive effect from the numerical simulation are shown, useful to understand piezoresistive effect which is difficult to see by experimental results.

Energy harvesters, such as photovoltaic cells, generate carriers in the deep substrate regions; these carriers can affect MOSFETs and deteriorate their performance or even cause malfunctioning. In this study, we discussed the effects of bulk carrier contamination on integrated MOSFETs in the context of energy-harvesting devices. We confirmed that the close integration of MOSFET circuits in a photovoltaic cell causes malfunctioning under strong light illumination. Moreover, numerical simulations revealed that PMOS is highly sensitive to carrier contamination as a forward pn-junction from the bulk-side storage carriers into the NWell region. Furthermore, increasing the distance from the illumination window was not an effective countermeasure, and alternative methods, such as the silicon-on-insulator substrate, n - substrate, or NMOS logic, should be implemented for such large-scale integration.

This study discusses the effect of stress on 4H-silicon carbide (4H-SiC) power diodes using numerical simulations. Two power diodes were evaluated; namely, a 600 V PiN diode and 1.8 kV junction barrier Schottky (JBS) diode. Stress changes the carrier mobilities in the material of the PiN diode of a bipolar diode; that is, the mobility is enhanced by the piezoresistive effect, which minimizes the on-resistance or leakage current. The simulation results demonstrate that compressive stress can have a positive effect on the device operation, particularly in p+-substrate power diodes. Regarding the JBS diode, the GPa-order tensile stress positively effects both forward and reverse characteristics. A cantilever structure is suitable for JBS diodes, and press-pack packaging for PiN diodes can enhance the device characteristics.

As a replacement for conventional silicon (Si), the germanium (Ge) materials have attracted interest because Ge provides larger carrier mobility and is advantageous for high-speed switching. In this study, the silicon-germanium (SiGe) ultrashort-gate transistor performances were studied using electrical-Thermal analysis. The material properties of SiGe can be modified by regulating the mole fraction in Si1-xGe1-x, and the different material characteristics affect the nanoscale transistor performance because channel regulation strongly depends on the bandgap energy. This study aims to reveal the structural and material designs of SiGe transistors to ensure sufficient performance and reliability.

In recent years, Internet of Things (IoT) has become more and more important owing to the rapid expansion of the number of computing devices and data sizes. The evolution of IoT requires low-power and self-operating devices to expand the coverage area of computing resources. The main components of IoT are the large-scale integration (LSI) chips, which take the function of implementing the energy harvesters, control units and applications. They exhibit different physics or phenomena, making it difficult to understand and design the entire system. The current work reviews the various methods for IoT applications by CMOS LSI chips, from the power components by energy harvesting to realistic applications with future outlooks.

This study proposes a sub-kHz clock generator by the room light illumination designed on-chip CMOS LSI chips. It generates a clock from a flicker in room light by receiving on-chip integrated photovoltaic cell, and extracts by low-pass filters, a comparator, Schmidt trigger and D-flip-flop to shape to digital signal. The system implements two photovoltaic cells of a large cell for power generation and a small cell for photo-detection that enables standalone operations. The system was designed on 0.18 $μm$ standard CMOS process, and both the simulation and experimental results validated the operation. By adding D-flip-flops at the output enables to modify the clock to $1/n$ values that expands the applications