論文

Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today's technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as FPGAs, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for Reconfigurable Kernels and Systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

Integrating FPGAs to robot systems can be a demanding task. In this paper we present Forest, an open-source tool that automatically generates ROS2 nodes for high-level synthesis-based FPGA modules, greatly facilitating the integration of FPGAs with other robot components. Forest runs on the PYNQ version 2.5 environment with ROS2 Eloquent and can be used with Xilinx SoCs, such as Xilinx Zynq-7000. The ROS2-FPGA node generated by Forest is evaluated in an image processing task, where the FPGA logic performs a linear contrast stretch on images of three different sizes, and an average speed-up of 36.3x and a performance per watt improvement of 432.2x is observed when compared to a ROS2 node running on a modern CPU.

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

Sensor nodes used in Internet of Things (IoT) are required to work an extremely long time without replacing the battery. Natural renewable energy such as a solar battery is a hopeful candidate for such nodes. Here, a power model for operating an Silicon on Insulator (SOI) device with a solar battery including a large inner resistance is proposed, and applied to a micro-controller V850E-star and an accelerator CMA-SOTB2. Unlike the ideal case, the maximum operational frequency was achieved with reverse biasing by suppressing the leakage current which decreases the supply voltage. Under the room light with a large inner resistance, the strong reverse bias is effective, while a relatively weak reverse bias is advantageous under the bright light. The proposed model is appeared to be useful to estimate the appropriate body bias voltage both for V850E-star and CMA-SOTB2. In the V850E-star, the estimated operational frequencies were different from the real chip, while they were relatively matched when CMA-SOTB2 was used under the low illuminance.

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as Coarse-Grained Reconfigurable Architectures (CGRAs). Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work. Experimental result shows the proposed method can solve the problem within 0.5 sec for all benchmarks in any conditions and demonstrates up to 5.65x speed-up compared to the previous method with negligible loss of accuracy.

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design.

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

This paper describes the software system for the building block computing systems. The programs on the system are executed by the building block OS that manages configuration information of the 3D stacked chips and virtualizes the accelerators as the OpenCL functions. In addition, the OS controls the power supply of the chips implemented with SOTB (Silicon on Thin Box). This paper introduces the basic concepts and functions of the software systems for the building block computing systems.

PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.

High performance of Machine Learning algorithms has enabled numerous applications based upon speech interface in our daily life, but most of the frameworks use computationally expensive algorithms deployed on cloud servers as speech recognition engines. With the recent surge in the number of IoT devices, a robust and scalable solution for enabling AI applications on IoT devices is inevitable in form of edge computing. In this paper, we propose the application of Systemon-Chip (SoC) powered edge computing device as accelerator for speech commands classification using Convolutional Neural Network (CNN). Different aspects affecting the CNN performance are explored and an efficient and light-weight model named as CASENet is proposed which achieves state-of-the-art performance with significantly smaller number of parameters and operations. Efficient extraction of useful features from audio signal helped to maintain high accuracy with a 6X smaller number of parameters, making CASENet the smallest CNN in comparison to similarly performing networks. Light-weight nature of the model has led to achieve 96.45% validation accuracy with a 14X smaller number of operations which makes it ideal for low-power IoT and edge devices. A CNN accelerator is designed and deployed on FPGA part of SoC equipped edge server device. The hardware accelerator helped to improve the inference latency of speech command by a 6.7X factor as compared to standard implementation. Memory, computational cost and latency are the most important metrics for selecting a model to deploy on edge computing devices, and CASENet along with the accelerator surpasses all of these requirements.

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.

End-to-end network latency has become an important issue for big data processing on large-scale and heterogeneous data centers. To realize them, a low-latency inter-switch network is required. In recent years, a novel network based on a random regular graph such as Jellyfish has been proposed as a solution to these problems. To realize this network on Infiniband, we explore layered shortest path routing that guarantees deadlock freedom. Infiniband can avoid deadlocks by using Virtual Lane (VL), which is a QoS guarantee mechanism. However, the output VL is indirectly determined by using Service Level (SL) held by each packet. In this research, to minimize the number of consumed SLs, we propose an algorithm based on a graph coloring problem to assign SLs to all source-destination pairs. The proposed method can reduce the number of consumed SLs by up to 38%compared to the conventional SL mapping method.

FiC (Flow-in-Cloud)-SW is an FPGA-based switching node for an efficient AI computing system. It is equipped with a number of serial links directly connected to other nodes. Unlike other multi-FPGA systems, the circuit switching fabric with the STDM (Static Time Division Multiplexing) is implemented on the FPGA for predictable communication and cost-efficient data broadcasting. Parallel convolution modules for AlexNet are implemented on FiC-SW1 prototype boards consisting of Kintex Ultrascale FPGA, and evaluation results show that the parallel execution with 20 boards achieved 4.6 times better performance than the state of art implementation on a single Virtex 7 FPGA board.

Flow-in-Cloud(FiC) is an acceleration platform designed to make a virtual monolithic large FPGA image from a number of mid-range economical FPGAs. We will show the live demonstration of the acceleration example of FiC with 24 boards through the network.

VPCMA (Variable Pipelined Cool Mega Array) is a low power CGRA (Coarse-Grained Reconfigurable Architecture) which we previously proposed in [1]. CC-SOTB2 is a real chip implementation of the VPCMA using Renesas 65-nm SOTB technology [2]. In this demonstration, we will show the power consumption of the CC-SOTB2 while performing a real image processing.

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

This paper aims at establishing a method for designing high-performance network topologies to bridge a gap between theoretical and practical studies. To this end, we present a novel graph called a host-switch graph, which consists of host vertices and switch vertices with maximum degree 1 and r, respectively. This graph represents a network topology of a practical parallel/distributed computer system with host computers connected by r-port switches. We discuss important metrics for designing high-performance interconnection networks: the host-to-host average shortest path length (h-ASPL) and the bisection width (BiW). In particular, we explore a method for constructing host-switch graphs with low h-ASPL and high BiW that connect the fixed number of hosts via any number of r-port switches. We demonstrate that the number of switches that provides the minimum h-ASPL can mathematically be approximated, and the minimum number of switches that provides a certain BiW can experimentally be approximated. On the basis of the approximations, we propose a randomized algorithm for searching host-switch graphs. We then apply the graphs to interconnection networks and compare them with typical network topologies. As compared with the torus, the dragonfly, and the fat-tree, our networks attain higher performance and smaller power and costs.

A host-switch graph was originally proposed as a graph that represents a network topology of a computer systems with 1-port host computers and (Formula presented.) -port switches. It has been studied from both theoretical and practical aspects in terms of the diameter, the average shortest path length, and the performance of real applications. In recent high-performance computing systems, however, a host computer is connected to multiple switches by using InfiniBand, NVSwitch, or Omni-Path, and consequently they provide high bandwidths. Since a host-switch graph cannot represent such systems, this article extends a host-switch graph so that it can represent such systems. As a result, a host-switch graph can include multi-ported hosts. Furthermore, we propose to use multi-port hosts for reducing the diameter. We show that the diameter minimization is equivalent to solving the degree diameter problem for bipartite graphs of diameter three. Our experimental results show that we can drastically reduce the diameter as well as increasing the bandwidth and improves performance of MPI applications by up to 162% as compared with networks with single-ported hosts.