論文

Machine learning- or neural network-based intrusion detection systems (IDSs) demonstrate the state-of-the-art performance and confidence in current threat detection. However, due to the increasing sophistication of today's network attacks and the growing cost of obtaining attack labels for network traffic, updating an IDS model with labeled data requires significant effort. Furthermore, in real-time developments of the Internet of Things (IoT), network flow input and large-size deep learning models impose additional latency and low throughput due to the hardware resource, bandwidth, and programming cost. To this end, this paper proposes an on-device sequential learning semi-supervised anomaly detector-based intrusion detection system (ONLAD-IDS) using smart interface network cards (NICs) to address these challenges. The ONLAD- IDS consists of packet sniffing, feature extractor, feature selection with analysis of variance (ANOVA), and an ONLAD model. Moreover, the real-time throughput ONLAD-IDS is developed by the Nvidia Bluefield DPU with smartNICs without programming cost. Experiments show that ONLAD-IDS achieves a throughput of 1486.095 packet/ms and a detection rate of 0.7523 on DPU with a 25Gb/s transmission throughput while maintaining high detection performance.

Neuromorphic computing has been getting attention because of its potential for fast and low-power computation, robustness, and learning capability. Though traditional machine learning applications are main target of neuromorphic computing, its characteristic of parallel and distributed processing with simple spike-based signals is useful for other types of applications such as a shortest path finding problem (SPFP) on a graph. Prior work discussed approaches for mapping SPFP to a spiking neural network (SNN). In this paper, we propose an SNN algorithm for path planning with moving obstacles. In real world situation, there are many moving obstacles (such as other cars for an autonomous driving car and human for a moving robot) around a target agent which tries to optimize its own path to the goal. Finding an effective path in such an environment is not an easy task since behavior of obstacles is sometimes unknown and there must be a huge number of candidate paths to go. Traditional methods for SPFP with a general CPU may not be effective since it should compare candidate paths and select the most suitable one every time step. We consider two agents with SNN which tries to achieve two goals: 'reaching its destination promptly' and 'avoiding moving obstacles properly'. Thanks to SNN properties, the agent can learn and estimate how the obstacles move. We compare the proposal approaches with an existing method on a 2D grid graph and the result shows that the proposal agents can select proper paths depending on obstacles' movement.

Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about 2.78 μW when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods because it has high fidelity and requires only nearest neighbor qubits connectivity. To realize FTQC, we need a decoder circuit capable of not only QEC in a 3-D lattice to deal with errors in measurement on ancillary qubits but also quantum operations on logically constructed qubits. Whereas several methods to perform logical operations on SC, such as lattice surgery (LS), are known, no practical decoders supporting them have been proposed yet.One of the most promising QC implementations today is made up of superconducting qubits that are located in a cryogenic environment. To reduce the hardware complexity of QC and latency of QEC, we are supposed to perform QEC in a cryogenic environment. Hence a power-efficient decoder is required due to the limited power budget inside a dilution refrigerator.In this paper, we propose an online-QEC algorithm that supports LS with a practical decoder circuit, as well as a new FTQC architecture. We design a key building block of the proposed architecture with a hybrid of SFQ- and Cryo-CMOS-based digital circuits and evaluate it with a SPICE-level simulation. Each logic element includes about 2400 Josephson junctions, and power consumption is estimated to be 2.07 μW when operating with a 2 GHz clock frequency. We evaluate the decoder performance by a quantum error simulator for an essential operation of LS with code distances up to 11, and it achieves a 0.6% accuracy threshold. In an LS-based architecture further supporting a magic-state distillation protocol, which is expected to run for near-term universal quantum computing, we evaluate the QEC performance and power consumption of the architecture and show that it is practical to be operated in 4-K temperature region of a dilution refrigerator.

Edge computing aims to handle the data very close to the source where it is produced, and also provides an effective way to alleviate the burden of cloud computing for the processing of massive volume of data, enabling lower latency, faster response, and more comprehensive data analyses. Meanwhile, graph-based data has emerged especially in the form of social networks, World Wide Web (WWW), transportation, biological networks, and so on, which become high-impact domains of human activity to build smart society. Generally, as the resources on compact end devices are strictly constrained, a graph processing solution with low latency and low overhead is a real necessity for graph analytics in edge computing. In this paper, for the first time to our knowledge, we propose a lightweight interactive graph processing library (GPL) for edge computing in smart society, which is user-friendly and handy to be operated on a single device or among multiple devices. Evaluation is conducted to indicate that the proposed GPL is highly competitive with other established libraries such as igraph, NetworKit or NetworkX based on different graph datasets over a variety of popular algorithms.

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as coarse-grained reconfigurable architectures. Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work based on an integer linear program. Experimental result shows the proposed method can solve the problem within 0.5 s for all benchmarks in any conditions. For a middle-class problem, up to 5.65- speedup and a geometric mean of 2.06 - speedup are demonstrated compared to the previous method with negligible loss of accuracy. Besides, we explore finer body bias control considering the power- and area-overhead of an on-chip body bias generator and suggest the most reasonable design saves 66% of energy consumption.

Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware way to provide the capacity-constrained portable terminals with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of the human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transportation, Internet of Things (IoT), etc. These application domains often manage a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize complex problems where graph-based data is involved. In consideration of the relatively insufficient resource provisioning of the edge devices, in this paper, for the first time to our knowledge, we propose a reliable edge-cloud collaboration framework that facilitates the graph primitives based on a lightweight interactive graph processing library (GPL), especially for shortest path search (SPS) operations as the demonstrative example. Two types of different practical cases are also presented to show the typical application scenarios of our graph processing strategy. Experimental evaluations indicate that the acceleration rate of performance can reach 6.87x via graph reduction, and less than 3% and 20% extra latency is required for much better user experiences for navigation and pandemic control, respectively, while the online security measures merely consume about 1% extra time of the overall data transmission. Our framework can efficiently execute the applications with considering of user-friendliness, low-latency response, interactions among edge devices, collaboration between edge and cloud, and privacy protection at an acceptable overhead.

Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware paradigm to provide them with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transports, Internet of Things (IoT), etc. These application domains often handle a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize complex problems in which the graph-based data is involved. In view of the relatively insufficient resource provisioning of the portable terminals, in this paper, for the first time to our knowledge, we propose an interactive and reductive graph processing library (GPL) for edge computing in smart society at low overhead. Experimental evaluation is conducted to indicate that the proposed GPL is more user-friendly and highly competitive compared with other established systems, such as igraph, NetworKit and NetworkX, based on different graph datasets over a variety of popular algorithms.

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as Coarse-Grained Reconfigurable Architectures (CGRAs). Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work. Experimental result shows the proposed method can solve the problem within 0.5 sec for all benchmarks in any conditions and demonstrates up to 5.65x speed-up compared to the previous method with negligible loss of accuracy.

Wide spread of IoT devices has made it possible to acquire enormous amounts of realtime sensor information. Due to the explosive increase in the sensing data volume, it becomes difficult to collect and process all the data in one central place. On one hand, storing and processing data on edge devices, so called edge computing, is becoming important. On the other hand, edge devices usually have only limited computing and memory resources, and hence it is not practical to process and save all the acquired data. There is a great demand of effectively selecting data to process on an edge device or to transfer it to a cloud server. In this paper, we propose an efficient density-based data selection and management method called O-D2M by which edge devices store the data representing inherent data distribution. We use a low cost graph algorithm to analyze input data trend and its density. We evaluate effectiveness of the proposed O-D2M comparing to other methods in terms of the accuracy of machine learning models trained by the selected data. Throughout the evaluation, we confirm that O-D2M obtains higher accuracy and lower computation cost while it can reduce the amount of data to be processed or transferred by up to 20 points.

Due to the slowdown of Moore's Law, power limitation has been one of the most critical issues for current and future HPC systems. To more efficiently utilize HPC systems when power budgets or deadlines are given, it is very desirable to accurately estimate the performance or power consumption of applications before conducting their tuned production runs on any specific systems. In order to ease such estimations, we showcase a straight-forward and yet effective method, based on the enhanced power management framework and DSL we developed, to help HPC users to clarify the performance and power relationships of their applications. This method demonstrates an easy process of profiling, modeling and management on both performance and power of HPC systems and applications. In our evaluations, only a few (up to 3) profiled runs are necessary before very precise models of HPC applications can be obtained through this method (and algorithm), which has dramatically improved the efficiency of and lowered the difficulty in utilizing HPC systems under limited power budgets.

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

The supercomputer, “Fugaku”, which ranked number one in multiple supercomputing lists, including the Top500 in June 2020, has various power control features, such as (1) an eco mode that utilizes only one of two floating-point pipelines while decreasing the power supply to the chip; (2) a boost mode that increases clock frequency; and (3) a core retention feature that turns unused cores to the low-power state. By orchestrating these power-performance features while considering the characteristics of running applications, we can potentially gain even better system-level energy efficiency. In this paper, we report on the performance and power consumption of Fugaku using SPEC HPC benchmarks. Consequently, we confirmed that it is possible to reduce the energy by about 17% while improving the performance by about 2% from the normal mode by combining boost mode and eco mode.

We evaluated the A64FX processor used in the supercomputer Fugaku using the SPEC CPU and SPEC OMP benchmark suites. As a result, we found the performance of the A64FX processor, which had 48 cores, was lower than that of the Xeon with dual sockets of 24 cores each in SPEC CPU int and fp. In SPEC OMP, due to the effect of the Xeon's Hyperthread, the A64FX performance was lower than the performance of the Xeon with single socket of 28 cores. But in several benchmarks in SPEC CPU fp and SPEC OMP, the A64FX performance was higher due to its high memory bandwidth. In addition, by comparing the performance and power using the power control mechanism of the A64FX, it was confirmed that power can be reduced without affecting the performance when not using all cores.

Graph-based simultaneous localization and mapping (G-SLAM) is an intuitive SLAM implementation where graphs are used to represent poses, landmarks and sensor measurements when a mobile robot builds a map of the environment and locates itself in it. Being a very important application employed in many realistic scenarios, estimating the whole environment and all trajectories through solving graph problems for SLAM can incur a large amount of computation and consume a significant amount of energy. For the purpose of improving both performance and energy efficiency, we have unveiled the critical path of the G-SLAM algorithm in this paper and implemented a GPU-based solution to aid it. Furthermore, we have attempted to offload performance-critical components (such as matrix inversions when updating the trajectory) in the G-SLAM process into GPUs through CUDA to exploit data parallelism. With our solution, we observe a speed-up of up to 19.7x and an energy saving of up to 83.7% over a modern workstation class x86 CPU; while on a platform dedicated for edge computing (NVIDIA Jetson Nano), we achieve a speed-up of up to 2.5x and an energy saving of up to 6.4% with its integrated GPU, respectively.

The idea of using inexact computation for overprovisioned DNNs (Deep Neural Networks) to decrease power and la-tency at the cost of minor accuracy degradation has become very popular. However, there is still no general method to schedule DNN computations on a given hardware platform to effectively implement this idea without loss in computational efficiency. Most contemporary methods require specialized hardware, ex-tensive retraining and hardware-specific scheduling schemes. We present FAWS: Fault-Aware Weight Scheduler for scheduling DNN computations in heterogeneous and faulty hardware. Given a trained DNN model and a hardware fault profile, our scheduler is able to recover significant accuracy during inference even at high fault rates. FAWS schedules the computations such that the low priority ones are allocated to inexact hardware. This is achieved by shuffling (exchanging) the rows of the matrices. The best shuffling order for a given DNN model and hardware fault profile is determined using Genetic Algorithms (GA). We simulate bitwise errors on different model architectures and datasets with different types of fault profiles and observe that FAWS can recover up to 30% of classification accuracy even at high fault rates (which correspond to approximately 50 % power savings).

With the increase and diversity of network attacks, machine learning has shown its efficiency in realizing intrusion detection. Federated Learning (FL) has been proposed as a new distributed machine learning approach, which collaboratively trains a prediction model by aggregating local models of users without sharing their privacy-sensitive data. Recently, the approach is applied to optimize intrusion detection for resourced-constrained environments. However, since the attacks are becoming more sophisticated and targeted, there is also a growing need to enhance detection models according to the characteristics of attack type; meanwhile, choosing effective feature sets from the network traffic characteristics is considered one of the most important technologies in data analysis. In this paper, we first proposed a federated learning-based intrusion detection system with feature selection technology. Firstly, a greedy algorithm is suggested to select features that achieve better intrusion detection accuracy regarding different attack categories. Afterward, multiple global models are generated by the server in federated learning, according to the decided features of edge devices. For evaluating the effectiveness of the proposed approach, simulation experiments based on the latest on-device neural network for anomaly detection are conducted over the NSL-KDD dataset. Experimental results demonstrate greatly improved accuracy of our method.

Sound field rendering is computation-intensive and memory-intensive. This research investigates an FPGA-based accelerator for sound field rendering with an FDTD scheme, in which wave equations are directly implemented by reconfigurable hardware, and spatial blocking is applied to alleviate the memory bandwidth requirement. Compared to software simulation performed on a desktop machine with 128 GB DDR4 RAMs and an Intel i7-7820X processor running at 3.6 GHz, the proposed FPGA-based accelerator achieves up to 2.98 times more in computing performance in the case of different layer sizes and different numbers of nodes computed in parallel even though the FPGA system runs at about 267 MHz.

Data structure is the key in Edge Computing where various types of data are continuously generated by ubiquitous devices. Within all common data structures, graphs are used to express relationships and dependencies among human identities, objects, and locations; and they are expected to become one of the most important data infrastructure in the near future. Furthermore, as graph processing often requires random accesses to vast memory spaces, conventional memory hierarchies with caches cannot perform efficiently. To alleviate such memory access bottlenecks in graph processing, we present a solution through vertex accesses scheduling and edge array re-ordering, in parallel with the execution of graph processing application to improve both temporal and spatial locality of memory accesses, especially for edge-centric graphs which are popular means in handling dynamic graphs. Our proposed architecture is evaluated and tested through both trace-based cache simulations and cycle-Accurate FPGA-based prototyping. Evaluation results show that our proposal has a potential of significantly reducing the quantity of Miss-Per-Kilo-Instructions (MPKI) for Last Level Cache (LLC) by 56.27% on average.

Shortest path problem is a problem of finding a path that minimizes the cost of connecting two nodes in a weighted graph. A∗algorithm for solving shortest path search has been applied in various fields such as path navigation systems, automatic robot planning and VLSI design. However, in recent years, the scale of graphs has become large. We need to solve the problem faster and with less power consumption. In this study, we propose a hardware accelerator for solving the shortest path problem using A∗algorithm based on HDA∗(Hash Distributed A∗) using FPGA. In evaluation we compare execution time and power consumption between CPU, GPU and FPGA. FPGA was able to solve Maze problem using the least amount of power. The energy efficiency of FPGA was up to 9 times higher than that of CPU.