Published papers

Short-distance (<10cm) wireless communications applications are rapidly expanding. For instance, a fast file transfer by "touch-and-proceed data communication" provides a user-friendly interface for electronic products [1,2]. Wireless I/O's may replace conventional connectors on a PCB to overcome performance limitations [3,4]. High-speed (>Gb/s), low energy dissipation (<100pJ/b), low bit-error-rate (BER<10 -3), and low cost (small layout area in matured CMOS processes) are required as well as compliance with spectral regulation and EMI/EMS. None of the previous research achievements has satisfied all these requirements (Fig. 26.2.6). Non-coherent UWB transceivers are typically low speed and energy hungry; i.e. 15Mb/s with 2680pJ/b in a heterodyne transceiver [1] and 1Mb/s with 373pJ/b in a direct-conversion transceiver [3]. Millimeter-Wave radio is often used to raise the data rate at the cost of increase in energy dissipation. A heterodyne non-coherent 60GHz transceiver performed 2.5Gb/s with 114pJ/b [2]. To further reduce the energy dissipation a direct-conversion coherent 56GHz transceiver was developed in 40nm CMOS and 11Gb/s was achieved with 6.4pJ/b [4]. Unfortunately, as a free-running TX LO and injection-lock carrier synchronization were employed, the injection locking range was very narrow. For an RF input power of -30dBm, the locking range was 60MHz, only 0.1% of the center frequency. Tight control of frequency under variation and noise is not easy for manufacturing. Raising the RF input power is also limited by the FCC spectral mask regulation. In this paper, we present a UWB direct-conversion coherent transceiver in 90nm CMOS. 2Gb/s with 75pJ/b is achieved while meeting the FCC regulation for indoor communications. An IQ-switching carrier recovery scheme is proposed to save layout area and energy dissipation by 43% and 20%, respectively, compared with those in the conventional Costas loop. The transceiver with the proposed carrier recovery scheme uses binary phase shift keying (BPSK) modulation. © 2012 IEEE.

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated. © 2011 IEEE.

An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target data rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The maximum data rate of the inductive-coupling link demonstrated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal data rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a data rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult. ©2010 IEEE.

This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision. © 2012 IEEE.

This paper introduces low-power and small area injectionlocking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2-V supply at 12.5 Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87 ps. The CDR area is 0.165 mm2.

A low-power and high accuracy comparator based on voltage controlled ring-oscillator (VCO) is presented. By using the dead zone of phase detector effectively, the VCO comparator automatically changes its noise level depending on the input voltage level (Δvin). When Δvin is large, the comparator operates as a low-power delay-line based comparator. On the other hand, when Δvin is small, the VCO is enabled and eye is opened during the oscillation. This suppress input referred noise and enables accurate conversion. The number of oscillation cycle for one comparison is inversely proportional to Δvin and adaptive noise reduction is realized. The VCO comparator does not require any sort of tuning. A 13b SAR ADC with proposed VCO based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves SNDR 66 dB at 1 MS/s with FoM of 29fJ/conv.-step.

A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.

This paper presents a small size, low-power inductive-coupling receiver for wireless proximity communication. Area efficient active inductor peaking is used to expand the bandwidth of low voltage LNA. Proposed LNA can operate intermittently, synchronized with received pulse timing and reduces the power consumption at low data rate. Clock is extracted from the received pulse signal by simple combination of imbalanced inverters. The fabricated test chip in 65nm-CMOS occupies 0.035mm2 and achieved 1.6Gbps with power consumption of 1.76mW at 0.8V power supply. © 2013 IEEE.

This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2. © 2013 IEEE.

This paper presents a pulse-based inductive-coupling transceiver with adaptive pulse width controller for high-speed wireless proximity communication. Adaptive pulse width controller uses 20 phase clocks generated by a multi-phase digitally-controlled-array-oscillator and prevents the pulse width fluctuation under PVT variation at ultra-low power supply voltage. Pulse generation and its width detection are carried out by the identical multi-phase oscillator, which reduces the circuit area. The test chip implemented in 65nm-CMOS has achieved data rate of 850Mb/s/ch at 0.7V supply voltage and power consumption of 4.1mW. © 2012 IEEE.

This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on LNA only at the moment when the pulse signal appears is used to reduce power consumption. To optimally control the On-time of LNA, pulse width detector based on self-oversampling TDC is used and compensate the PVT variations of On-time witdh and of pulse signal width. The fabricated test chip in 65nm CMOS occupies 0.06mm2 and achieved the intermittently operating frequency at the range from 60 to 400Mbps. The power consumption is 0.42mW at 400Mbps and the supply voltage of 0.7V which corresponds to 37% power reduction from the power consumption without optimal On-Time Controller. © 2013 IEEE.

This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is 104dB with sampling capacitor of 1.28pF. © 2010 IEEE.

An all-digital CDR for a pulse-based inductive-coupling interface is presented, which uses a TDC with free running oscillator for seamless oversampling and an all-digital DLL. The TDC utilizes an error correction scheme to reject noise pulses and the DLL recovers the phase information based on a 32-bit digital comparator. Peak-to-peak jitter is 12.2ps with 1.2Gb/s at 1.2V, whereas energy consumption is 4.7pJ/b with 1.2Gb/s at 0.6V. © 2011 IEEE.

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (rm HVt) and low threshold voltage (rm LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s. © 2013 IEEE.

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2. © 2012 IEEE.

This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz. © 2010 IEEE.

As silicon chip performance continues to increase, the interconnection capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical directional coupler (VDC), which has actually been applied to a liquid crystal display (LCD) driver board. The feasibility of a millimeter-range non-contact interface using a directional coupler was studied previously [1]. In this paper, two signal ports have been implemented in one coupler by best utilizing the characteristics of VDC. The coupler size is 5mm × 2.25mm, and the gap between the couplers is about 75μm, which corresponds to the twofold thickness of a soldering resist on PCB and the adhesive material in between. The transmitter transforms the data sequence from Non-Return-to-Zero (NRZ) into pulses in order to reduce the level of DC components. This achieves a power saving of 1.47pJ/b, and the pulses are sent to the coupler in differential mode to prevent electromagnetic interference (EMI). The measured speed was 4.6Gb/s per coupler to achieve the MIPI's maximum speed of 6Gb/s with two couplers. Conventional connectors have housings to protect contact elements or to provide mechanical support for plug-in and out. However, these housings make it difficult to achieve the smallest possible systems because they require extra space. In addition, they sometimes make the PCB trace longer, which deteriorates the maximum data rate. The method we have developed involves delineating VDC on PCB or a flexible printed circuit (FPC) to connect boards without housings and with the minimum distance. As a result, this interconnect scheme is advantageous not only because it saves space but also because it makes it easier to build systems, even those that contain a large number of built-in connectors. Thus, the proposed non-contact interconnect is suitable for future small-size systems. © 2013 IEEE.

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2013 IEEE.