Published papers

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2012 IEEE.

In this paper, a 13.56 MHz fully-integrated wireless power transfer system with wireless constant-idle-time control is proposed. The massive off-chip components or wire required for transmitter (TX) voltage regulation in previous works are eliminated. Both wireless and local regulations are achieved with enhanced transient performance and total efficiency, and reduced circuitry and system design complexity. Thanks to the proposed wireless constant-idle-time control technique, an instant load-transient response, and a peak total efficiency of 67.6% with up to 13.7% improvement are observed in measurements with meat between coils at a distance of 6mm.

This paper presents a pulse-based inductivecoupling transceiver in 65nm CMOS for high-speed wireless proximity communication. The transceiver operates at 0.5V supply voltage. A pulse bootstrap circuit and a common drain output stage enables transmitter to operate at ultralow voltage. In the receiver, a gain boosted common-gate amplifier is used to reduce the input impedance and suppress the ringing of received pulse signal. The data rate and energy efficiency are 1.1Gb/s/ch and 0.91pJ/bit, respectively at 0.5V supply voltage. The data rate can be increased to 1.7Gb/s/ch at 0.75V. © 2011 IEEE.

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

This paper studies the multipath interference in a 2D multi-hop wireless power transfer system which uses magnetic resonance in two dimensional repeater array. By focusing on the current amplitude and phase in each repeaters, power combination from different path is discussed and simplified path interference model is proposed. The accuracy of the proposed simplified path interference model is compared with electromagnetic field simulation.

A 2nd order discrete time (DT) ΔΣ modulator with very wide supply voltage range of 0.25-1.8 V is presented. An inverter-opamp self-configuring amplifier (IOSA) is proposed with sufficient gain through sub-threshold to strong inversion region. The amplifier senses the supply voltage and automatically configures either to operate as an inverter or an opamp. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a best FoM of 0.09 pJ/step. At 1.8 V supply the modulator achieves SNDR 61dB and operates down to 0.25V. © 2013 IEEE.

A 65-nm CMOS-technology-based surface-acoustic-wave filterless transmitter (TX) for a long-term evolution (LTE) system was developed and performance tested. The TX incorporates both a passive quadrature modulator (QMOD) using bandpass filter (BPF)-based in-phase/quadrature (I/Q) signal summing and a small triple-layer Marchand balun. The passive operation and BPF-based I/Q summing, respectively, contribute to low noise performance and high input impedance (seen from the baseband signal), resulting in low receiver (RX) band noise and high linearity of the TX. The triple-layer Marchand balun contributes to the small area of the TX. A prototype LTE TX using the QMOD and the balun exhibits in-specification RX-band noise (<-161.6 dBc/Hz), a high output third-order intercept point (OIP3=20.5 dBm), and a small chip area (0.224 mm2).

A SAW-filter-less LTE transmitter based on 65-nm CMOS technology, incorporating a passive quadrature modulator (QMOD) with band-pass-filter (BPF) I/Q summing technique, was developed. The passive operation and the BPF I/Q summing technique, respectively, contribute to low noise performance and high input impedance seen from baseband signal, resulting in low receiver-band noise and high linearity of the transmitter. A transmitter using the QMOD exhibits both inspecification receiver-band noise (<-156 dBc/Hz) and high output 3rd intercept point (OIP3 = 20.6 dBm).

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL). ©2010 IEEE.

This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit. © 2011 IEEE.

This paper presents an ADC with programmability between SAR-only mode and delta-sigma (δΣassisted mode. The ?assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in δΣloop and improve the accuracy. The prototype ADC fabricated in 65- nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by δΣassisted mode when the signal bandwidth is 60 kHz.

This paper presents a low power, small area Frequency Acquisition Circuit (FAC) for a pulse-based inductive coupling transceiver. A multiphase clock which is generated in array oscillator is used to control the pulse width. To solve the problem of oscillation frequency change by PVT variation, FAC is proposed to control the oscillation frequency. FAC uses the multiphase clock generated in array oscillator. By sharing the multiphase clock for both the pulse generation and the frequency control, low power and small area can be achieved. The fabricated test chip in 65nm CMOS occupies 0.045mm2. The array oscillator generates 1GHz, 20 phase clocks at the supply voltage of 0.8V. The RMS of cycle-to-cycle jitter is 3.3ps and the power consumption is 1.1mW. © 2013 IEEE.

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with 1 kΩ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain. © 2011 IEEE.

As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1. © 2012 IEEE.

This paper describes a system of single-inductor-dual-output (SIDO) wireless power delivery for mobile applications. By updating control signal in the feedback loop by every switching clock cycle, fast tracking to the load change is realized while spurious emission is suppressed by using pseudorandom-sequence PWM (PRS-PWM). Transmitter and receiver chips were fabricated in 0.18μm CMOS process and mounted on the wireless power transfer test board. The system achieved response time shorter than 10μsec. Two output voltages are regulated at 8V and 16V, and maximum efficiency of 41% was achieved when the total output power is 500mW.

This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB. © 2011 IEEE.

This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V. © 2012 IEEE.

A 280 Mb/s non-contact in-vehicle LAN system using electromagnetic clip connectors is presented. The bidirectional transmission line coupler based electromagnetic clip connector, which can be used to make local area network connections similar to clips, suppresses the signal reflections on the bus enabling 280 Mb/s data rate which is 7 times faster than the state-of-the-art in-vehicle LAN transceiver. Since all modules are connected with the shortest distance, this connection system can reduce wire harness weight by 30%. Forward error correction is done by N-x Manchester encoding on the transmitter side and majority voting on the receiver side. High noise immunity is achieved through synchronous receiving by the digital clock recovery circuit which is robust against noise. Communication tests were conducted at 280 Mb/s with 10 transceivers fabricated in 65 nm CMOS technology connected by a 10 m unshielded twisted pair cable. Evaluation of the bit error rate and radiation spectrum confirmed that the ISO specifications concerning electromagnetic susceptibility and the CISPR ones concerning electromagnetic interference are satisfied.