Misc

A solid-electrolyte switch ("NanoBridge") has been successfully embedded into a 0.13-μm-node dual-damascene Cu interconnect using a highly reliable bilayer solid-electrolyte (TaSiO/Ta_2O_5) and a thin oxidation barrier, resulting in an excellent ON/OFF ratio (> 10^9) at a low ON resistance of 50Ω. The newly developed bilayer solid-electrolyte has improved the thermal stability during the BEOL process as well as improved electrical breakdown. The CMOS compatible NanoBridge is a promising switch to achieve high-performance and low-cost programmable LSIs.

Plasma polymerization method is developed for deposition of divinely siloxane bis-benzicyclobutene (BCB), as low-k organic material, with low dielectric constant and high thermal stability. The thermal stability of Plasma-polymerized BCB (p-BCB) polymer is improved over 400℃, the dielectric constant also improved K=2.6 Barrier-metal-free (BMF), Cu dual-damascence interconnects are fabricated in the p-BCB polymer film, which is featured by the anti-diffusive characteristics for the Cu. The BMF-structure has lower inter-line capacitance, keff=3.1, and higher operation speed than a conventional barrier-inserted structure, about 20%. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance of 50% to the conventional Cu/barrier/Cu contacts. The via-resistance with the structure will be achieved under 1Ω/via in the 0.1μm generations.

Fully-scaled-down,65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm^φ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDl via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDl with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDls with k_〜3.0 is applicable especially for the 65nm-node, low-power ASICs.

Suppression of interconnect RC delay has become very important for 0.1 μm-generation CMOS. The key is how to make Cu dual damascene interconnects in low-k film with keeping large misalignment tolerance. This paper describes a new dual hard mask (dHM) process with via-sidewall hardening chemistry for partial via etching to the low-k organic film without any high-k etch-stop layers By dual hard mask (dHM) process combined with sidewall-hardening plasma-etching, Cu dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low -k structure has the low via resistance such as 0.8Ω/0.28μmφ-via with keeping the large tolerance of misalignment up to 0.1 μm-far in via/trench, appreciable for 0.1 μm-generation CMOS ULSIs.

By a novel oxygen absorption process, low-oxygen-content (LOC) Cu-alloy is implemented for fully-scaled-down, 45nm-node dual damascene interconnects (DDIs) with 140nm-pitched lines and 70nm^φ-vias. In this process, a very thin metal film as an oxygen absorber, which has larger negative change in the standard Gibbs free energy of oxidation than a barrier metal, is put on a natural oxide at a surface of electro-plated, Cu film. The oxygen atoms diffuse to the oxygen absorber, not to the barrier metal under the Cu film, achieving high quality Cu/barrier interface after annealing. Combining the oxygen absorption process with Cu-alloy process, 45nm-node DDI in molecular-pore-stacking (MPS) SiOCH film is successfully obtained with high endurances for SIV, EM and TDDB.