Presentations

© 2016 EPFL. This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2 footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

A highly reliable, 65nm-node Cu interconnect technology has been developed with 180nm/200nm-pitched lines connected through φ100nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-intra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Highly thermal-stable, plasma-polymerized divinyl siloxane bis-benzocyclobutene (p-BCB) polymer film is developed for Cu dual-damascene interconnects. The thermal stability of p-BCB is improved over 400 °C by higher deposition temperature, having high resistance to Cu diffusion at 400 °C-annealing. Lowering the RF plasma-power and the deposition pressure, the p-BCB film has smaller dielectric constant than the conventional spin-coating BCB (k = 2.7). The p-BCB (k = 2.6)/Cu interconnects reveal 46% delay reduction of CMOS ring oscillator to the conventional SiO2/Al ones. The p-BCB is proved as a strong candidate for Cu/low-k interconnects.

The highly reliable low-k/Cu dual damascene interconnects (DDI) with in-situ fluorinated carbon-nitride (FCN) barrier was successfully obtained in an organosiloxane film. Using CxFy/N2-base plasma, the DDI etching is achieved by sidewall- deposited flurorocarbon polymers. In addition, the etched-surface is covered with the FCN barrier, which suppresses the Cu diffusion.

Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nmφ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with keff ∼3.0 is applicable especially for the 65nm-node, low-power ASICs.

A new plasma-enhanced organic monomer-vapour polymerization (plasma polymerization) method has been developed. It was used to make a divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer film for Cu dual-damascene interconnects that had high thermal stability and a low dielectric constant, k = 2.6. The method consists of the vaporization of organic monomers, transportation of monomers in the gas phase, and polymerization by plasma to make the polymer film. The method eliminates polymer oxidation of DVS-BCB during the polymerization in high vacuum, which improves the film's thermal stability. The thermal stability of plasma-polymerized BCB (p-BCB) exceeded 400°C because of the higher deposition temperature, and the film had a high resistance to Cu diffusion at 400°C annealing. The narrow-pitched Cu/BCB damascene lines showed a 35% reduction in line capacitance compared with Cu/SiO 2 ones. The p-BCB is shown to be a strong candidate for Cu/low-k interconnects.

The 45nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45nm-node ULSIs. © 2007 IEEE.

© 2020 IEEE. A nonvolatile FPGA using atom-switch crossbars is implemented in a 28nm CMOS. The depopulated atom-switch crossbar with double-gate layout achieves 75% area saving. The routability degradation due to the depopulation is mitigated by a modified routing architecture of mixed segment lengths with thinning out connection block populations. To our knowledge, the novel FPGA provides the largest logic capacity of 171k lookup-table (LUT) among 3D-FPGAs based on monolithically integrated nonvolatile switch and memory. The operating frequency and dynamic power are significantly improved as compared to conventional atom-switch FPGAs.

Barrier-metal-free (BMF), Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is featured by the anti-diffusive characteristics for the Cu. The BMF-structure has inter-line leak current as low as that of a conventional barrier-inserted structure and is estimated to keep the high insulating property over 10 years under 1MV/cm. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance of 50% to the conventional Cu/barrier/Cu contacts. The effective dielectric constant was keff=3.1 including very thin SiN etch-stop-layers, accomplishing 20%-fast CMOS device operation to that of the conventional Cu-DDI in the SiO2 with Ta/TaN barriers. The BMF, Cu-DDIs buried directly in the p-BCB film is one of the ultimate structures for high performance, 0.1μm-CMOS devices and beyond.

Low-resistance Cu damascene interconnects have been developed with highly oriented PVD-Ru/TaN liner using a direct-plated Cu process. Texture of the direct-plated Cu on the Ru/TaN is strongly correlated with Ru(002) orientation, enriching Cu(111) texture comparable with a conventional plated-Cu film on seed-Cu/Ta/TaN. The resistivity of 0.2μm-wide direct-plated Cu lines with the highly (002)-oriented Ru/TaN liner at 20K is 12.4% lower than that of conventional Cu lines with Ta/TaN liner, meaning that the reduction of the resistivity in Cu lines with Ru liner at RT was achieved by smaller interface scattering besides the lower bulk resistivity of Ru than Ta. The orientation control of Ru liner is a key factor for the low-resistance Cu interconnects needed for scaled-down ULSI interconnects. © 2007 IEEE.