Misc

This paper describes a method of dynamically throttling processor speed using dynamic voltage scaling (DVS) technique for low power computing. We propose a micro-architecture level mechanism that detects performance imbalance between processor and memory and adjusts processor frequency to redress the imbalance. By the adjustment, the mechanism selects an optimal processor speed among several voltage/frequency setting points and thereby power consumption is reduced. We evaluate power saving and performance degradation for our proposed method by cycle level simulation. The evaluation results reveal that the method has potential to reduce a large portion of energy consumption with negligible performance loss.

Recently, performance disparity between processor and main memory is increasing.To remedy performance degradation caused by this problem, a new architecture called SCIMA, which has software controllable integrated memory has been proposed. So far, We have developed "hint-infomation" based automatic optimization compiler for SCIMA. This compiler enables efficient utilization of software controlled memory of SCIMA. At present, there are several embedded processors which have software-controllable on-chip memory in addition to data caches. In this paper, we investigated and evaluated whether our proposing compiler is also applicable for such processors.

In recently years, power consumption per performance has become more important. We propose to improve power performance by optimizing data transfer with on-chip RAM which is a substitution of cache. To confirm effectivity of our proposal, we evaluate power consumption with SH4 commercial processor. The evaluation indicates that using on-chip RAM makes data transfer optimal, and the optimization reduces about 15.2% EDP (Energy Delay Product) at the maximum. If SH4's on-chip RAM supports DMA between the on-chip RAM and main memory, it is estimated that the optimization reduces about 26.3% EDP at the maximum.

As semiconductor technology scales down, the static power due to leakage current becomes dominant in the total power dissipation of a microprocessor. Especially, cache memories dissipate a large portion of static power in the processor chip. Therefore, reducing leakage current in cache memories is very important. We have proposed a new processor architecture called SCIMA, which has integrated Software-Controllable Memory (SCM) on the processor chip in addition to the ordinary cache. Because unused part of the SCM can be identified by software, we can effectively reduce a large portion of static power by putting unused SCM part into low leakage mode. In this paper, we propose a leakage current reduction method using SCM, and show preliminary evaluation results.

As semiconductor technology scales down, the static power due to leakage current becomes dominant in the total power dissipation of microprocessors. We have proposed a static power reduction method for Software-Controlled Memory, which cut off the electric power supply of the unused SRAM cells. As for Software-Controlled Memory, there is a trade-off between the execution time and the area which are activated. Good trade-off point may change when energy consumption of other part on microprocessors are considered together. In this paper, we modeled the energy consumption of a microprocessor which has Software-Controlled Memory in order to find minimize the energy consumption of a total chip.

As semiconductor technology scales down, the static power due to leakage current becomes dominant in the total power dissipation of microprocessors. We have proposed a static power reduction method for Software-Controlled Memory, which cut off the electric power supply of the unused SRAM cells. As for Software-Controlled Memory, there is a trade-off between the execution time and the area which are activated. Good trade-off point may change when energy consumption of other part on microprocessors are considered together. In this paper, we modeled the energy consumption of a microprocessor which has Software-Controlled Memory in order to find minimize the energy consumption of a total chip.

今後，プロセスの微細化に伴いリーク電流が増大し，プロセッサ全体の消費電力に占める静的消費電力の割合が大きくなると予測されている．特にキャッシュはプロセッサの静的消費電力の多くを占めており，キャッシュにおけるリーク電流の削減は重要な課題である．そのため，近年ではキャッシュのリーク電流削減を目的とした回路的手法やマイクロアーキテクチャの研究が活発に行なわれている．一方，我々はキャッシュに加えソフトウェア制御可能なメモリをチップ上に搭載し，これを利用した高性能化を図るアーキテクチャSCIMAを提案している．ソフトウェアにより制御されるメモリ上では将来的にアクセスされる領域とアクセスされない領域を完全に特定できることから，アクセスされない領域を静的消費電力が少ないモードに切り替えておくことで，従来のキャッシュよりも効率的にリーク電流を削減できると考えられる．本稿では，SCIMAのこの特徴を利用したリーク電流削減手法について検討し評価を行った．As semiconductor technology scales down, the static power due to leakage current will increase and become dominant in the total power dissipation of microprocessors. Especially, cache memories dissipate a large portion of static power in the processor chip. Therefore, reducing leakage current in cache memories is very important. We have proposed a new processor architecture called SCIMA, which has integrated Software-Controllable Memory (SCM) on the processor chip in addition to the ordinary cache. Because unused part of the SCM can be identified by software, we can effectively reduce a large portion of static power by putting unused SCM part into low leakage mode. In this paper, we propose a leakage current reduction method using SCM, and show preliminary evaluation results.

In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip memories to achieve higher performance by utilizing on-chip memory. Because such properties are automatically controlled by hardware in conventional caches, a cost of optimization for a program becomes a matter that should be considered. In this paper, we propose an automatic optimizing compiler based on "Optimization Hint Informations". Using proposed compiler, users can optimize programs only providing hint informations for data reusability without any knowledge of architecture details. We evaluate the performance and cost of programming for our compiler using two applications. The results reveal that the proposed compiler can drastically reduce the programmers' burden and achieve high performance.

Recently, performance disparity between processor and main memory has increased. Serious performance degradation has often occurred especially in high-performance computing due to the disparity. To solve this problem, a new VLSI architecture called SCIMA has been proposed. SCIMA integrates processor and a part of main memory into a single chip. In this paper, we propose a directive based SCIMA compiler, and present a framework of the optimize compiler for SCIMA to realize automatic optimization using software-controlled On-Chip memory.

Recently, performance disparity between processor and main memory is increasing. To remedy performance degradation caused by this problem, a new memory architecture called SCIMA which has software controllable integrated memory has been proposed. SCIMA improves performance using software-contorllable memory. In this paper, we propose an algorithm of automatic optimizing compiler for SCIMA, and present preliminary evaluation of the proposed algorithm.