Published papers

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

The low-precision floating point arithmetic that performs computation by reducing numerical accuracy with narrow bit-width is attracting since it can improve the performance of the numerical programs. Small memory footprint, faster computing speed, and energy saving are expected by performing calculation with low precision data. However, there have not been many studies on how low-precision arithmetics affects power and energy consumption of numerical codes. In this study, we investigate the power efficiency improvement by aggressively using low-precision arithmetics for HPC applications. In our evaluations, we analyze power characteristics of the Poisson's equation and the ground motion simulation programs with double precision and single precision floating point arithmetics. We confirm that energy efficiency improves by using low-precision arithmetics but it is heavily influenced by parameters such as data division and the number of OpenMP threads.