Published papers

This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.

A 640 Gb/s high-speed ATM Switching System that is based on the technologies of advanced MCM-C, 0.25μm CMOS and optical WDM interconnection is fabricated for future B-ISDN services. A 40-layer, 160 mm × 114 mm Ceramic MCM realizes the basic ATM switch module with 80 Gb/s throughput. The basic unit ATM switch MCM-C consists of an 8-chip advanced 0.25 μm CMOS VLSI and 32 chip I/O bipolar VLSIs. The MCM employs a 40 layer, very-thin-layer ceramic MCM and a uniquely structured closed loop type liquid cooling system is adopted to cope with the MCM's high-power dissipation of 230 W. The MCM is mounted on a 32 cm × 50 cm mother board. A three-stage ATM switch is realized by optical WDM interconnection between the high-performance MCMs. For WDM interconnection, newly developed compact size 10 Gb/s, 8 WDM optical transmitters and receivers are used. An optical WDM router based on an AWG (Arrayed Waveguide Router) is used for mesh interconnection of boards. The optical WDM interconnect has 640 Gb/s throughput and easy, simple interconnection. The system, MCM, and Optical WDM interconnection will be applied to future B-ISDN backbone networks.

This paper presents new transfer schemes for client-server traffic over ATM networks, with the objective of achieving a bounded transmission time of about one second for as many connection requests as possible. We evaluate via simulations the performance of these new schemes in terms of network utilization, cell loss ratio, and transmission time. The simulation results show that these schemes provide effective means of supporting client-server traffic with quasi-real time requirements.

For an ATM switch system, we have developed a 100-Gb/s I/O throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25 μm CMOS ATM switch LSIs and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using 8 optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from DC to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.