Published papers

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4 × 2 switch module using optical interconnection technology and very high-speed crosspoint LSI's, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

This paper proposes Full-Net (Flexible Multi-QoS Logical ATM Network), a simple, flexible, and cost-effective network architecture that will enable the development of an advanced multimedia communications network. The backbone of this Full-Net is a VP (virtual path) network where mesh interconnection is made possible between all VCH (virtual channel handler) switches. End-to-end QoS (quality of service) control is executed at access points to the VP network to map out each optimum VC (virtual channel) according to the VCs' respective service characteristics. This is done independently and simultaneously on the same physical ATM network. In the proposed network, a relatively small size switching system is utilized as a transit switch or a local switch depending on the service request. That is, the logical topology of the VC network is altered in response to individual service requests, and multiple VC networks are realized by overlapping them on the same physical network. In order to assure high QoS and construct an optimum VC network, two parameters which characterize the VC network topology are introduced; one is the disjoint route D and the other is the hop limit H. Traffic reliability is the most important QoS factor, and it is shown that an optimum disjoint number D can be determined to maximize the network resource. In the Full-Net, it is clearly shown that it is possible to control easily the end-to-end delay characteristic, also a critical QoS factor, at one or two VCH access points to VP network. The flexible node system PUN (programmable unified node) used in the Full-Net is also described in this paper. The Full-Net described is proposed as an efficient solution for sophisticated network architectures which will satisfy the demand for new services and will flexibly meet the varying demands of the future multimedia age. © 1997 Scripta Technica, Inc.

Important breakthrough technologies for achieving several-hundred Gbit/s ATM systems are described. This paper presents a trend scenario to future B-ISDN networks and describes the technologies of very-high-speed ATM switching systems, including architecture, hardware, and traffic control.

This paper describes a 160 Gbit/s high speed multi-chip ATM switching system for broadband ISDN. This system uses a Copper/Polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layers ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a Multi-Chip Module (MCM) using the 15-μm very thin pitch outer lead TAB technique. The system switches ATM cells at a throughput of up to 320 Gbit/s and it is applicable for future B-ISDN.

An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polymide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching systems. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and con-nectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnections. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced air flow, a prototype ATM switch system operated at 320 Gbit/s (with 8 × 8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed switching systems.

As a switch architecture of the AMC with switch throughput of 160 Gbit/s, we proposed an internal speed-up crossbar-type ATM switch architecture. This switch accommodates 10-Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bidirectional arbiter, is used. This handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. This increases the switch throughput to 160 Gbit/s efficiently. By combining our high-speed switch and AHMs, we should be able to make a sub-terabit/s ATM switching system for the future Broadband ISDN network.

This paper describes a real-time emulation method based on the use of commercial FPGAs, high-speed interconnect switch devices and software tools (gate array LSI to/from FPGA netlist migration and multi-FPGA partitioning tools) to emulate large scale high-speed communication switching system without the need for conventional specific wiring structures between FPGAs and timing control circuit insertion. This method is applied to line interface units (LUs) that have 20 MHz operation; we employ the LU board and emulation boards, both of which have hierarchical structures with small sub-boards. The proposed LU board structure has the advantage of utilizing a common LU board for rapid prototyping as well as developing cost effective, practical high-performance Asynchronous Transfer Mode (ATM) switching systems for broadband ISDN (Integrated Services Digital Networks). The results of multiple FPGA partitioning on the emulation board suggest that the proposed method will yield economic systems that are also practical.

This letter proposes ALPEN, a simple, flexible and cost effective ATM-WAN architecture that emulates multiple ATM-layer protocols at the edge nodes. Any new ATMlayer protocol can be easily implemented by modifying only the edge nodes. The transit network is simple and independent of the protocols emulated, and ALPEN has a short response time. It is very suitable for implementing mutimedia ATM networks.

This paper proposes ALPEN, a simple, flexible and cost-effective ATM-WAN architecture that can emulate multiple ATM-layer protocols such as ABR, FRM, and SHM, using a simple ATM transit network. With ALPEN, it is easy to implement any new ATM-layer protocol by modifying only the edge nodes. Edge nodes are directly responsible for the management of the users' bandwidth, eliminating the long round trip delays of conventional networks. The transit network does not support multi ATM-layer protocols and ALPEN's transit switches do not need large computational power. Flexible, adaptive and sophisticated protocols for an efficient use of resources can be easily supported by the network's edge node. Users can then send as much traffic as permitted by the network's available bandwidth.

This paper describes a 160-Gbit/s high-speed multi-chip ATM switching system for broadband ISDN. This system uses a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layer ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a MCM using the 15-μ m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is used. The system switches ATM cells at a thoughtput of up to 320 Gbit/s and it is applicable for future B-ISDN.

This paper proposes simple and effective multi-QoS ATM buffer management scheme with admission control. The proposed scheme supports three QoS-service classes by two separate buffers with strict priority and measurement-based as well as individual CLR-based admission control. Two guaranteed classes for video and reliable data are multiplexed into a high priority buffer and individual CLR management is employed. We show that the proposed individual CLR management is simple and effective compared to separate buffers with WRR (weighted round robin). One best-effort class is assigned to the low priority buffer, and includes LAN intercommunication using upper-layer congestion control mechanism. Since measurement-based adaptive admission control is employed for best-effort service, the proposed adaptive admission control achieves high bandwidth efficiency while keeping the target CLR. This multi-QoS management scheme can be applied to future multimedia ATM networks that integrate video, data, and other services.

SUMMARY The benefits of ATM techniques have been widely recognized and many organizations envisage the introduction of ATM techniques into their telecommunication networks. The ATM benefits can, however, be fully exploited only after effective network resource management techniques have been developed. This paper focuses on CBR-VP management techniques. The ATM transport network architecture and VP roles are summarized. Next, the issues of VP accommodation design are described. The point is how to create a design that accommodates cell loss and cell delay jitter, both of which depend on various network parameters and conditions. For this purpose, analytical procedures based on an M/D/1 queueing model are adopted. The approximation method is shown to be very effective in practical use through computer analysis. The method guarantees conservative QOSs. Finally, the proposed method is applied to several design examples to illustrate VP management issues. The proposed method will enable ATM techniques to be introduced to our telecommunication networks by the mid.

This paper presents a migration scenario to future B-ISDN and describes the technologies of ultra-high-speed ATM switching systems, including architecture, hardware, and traffic control. Important breakthrough technologies for achieving several-hundred Gbit/s ATM systems are described.

An optimum design scheme is proposed for VC network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-networks access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. To achieve an optimum design scheme for VC networks, the number of disjoint routes is introduced as the parameter used to optimize VC network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand.

SUMMARY This letter studies the Peak Cell Rate (PCR) policing of ATM connections that consist of multiple cell flow components. It is shown that the conventional methods proposed for policing the aggregate flow do not use the network's resources efficiently. This letter proposes a simple and efficient UPC (Usage Parameter Control) mechanism based on a tandem leaky bucket for multi-component ATM connections. The results show that network resource requirements can be minimized, with reasonable hardware complexity.

A multicast ATM switch with a new external copy module is proposed. The copy module, called copy-trunk, has two new functions to guarantee the QoS of P-MP cells: The delay priority control function and the output-cell-spacing control function. By using the delay priority control function, copied cells with high-priority are always released earlier than those with low-priority so as to avoid increasing the delay time of real-time traffic. The output-cell-spacing control function is used to reduce the burstiness of the output traffic. The output pattern is adaptively controlled by measuring the input load. The effects of these two controls are quantitatively described. The copy-trunk allows the multicast capability of a switch to be efficiently and economically increased to satisfy future traffic volume and services.

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polyimide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching system. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and connectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnection. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced airflow, a prototype ATM switch system operated at 320 Gbit/s (with 8×8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed swithing systems.

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking.

This paper proposes a new topological design method, named BXCQ, which optimizes logical network configuration while guaranteeing QoS requirements for each service class in an ATM network. The BXCQ method determines the optimum logical network topology associated with each service class so as to minimize network cost. In our previously proposed Full-Net architecture[1], these different logical topologies can be suitably mapped at the same time on the same ATM physical network by using VCHs logical interconnection networks. According to the BXCQ method, the results quantitatively clarify the relations between multimedia traffic characteristics and desirable logical network configurations in the Full-Net. Evaluation results suggest that a service class that is bursty, delay tolerant and cell loss sensitive with small demand should be supported by a loop-like topology. Furthermore, the results also show that suitably changing logical configurations in accordance with traffic demand fluctuations leads to a dramatic reduction of 8.8% in network cost. This study will be useful for designing flexible and cost-effective multimedia networks that can also adapt to not-yet-known services.