Published papers

A back-propagation algorithm following a gradient descent approach is used for training deep neural networks. Since it iteratively performs a large number of matrix operations to compute the gradients, GPUs (Graphics Processing Units) are efficient especially for the training phase. Thus, a cluster of computers each of which equips multiple GPUs can significantly accelerate the training phase. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and parameter optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10 Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected via network switches, gradient aggregation and optimizers (e.g., SGD, Adagrad, Adam, and SMORMS3) are offloaded to an FPGA-based network switch between a host machine and remote GPUs; thus, the gradient aggregation and optimization are completed in the network. Evaluation results using four remote GPUs connected via the FPGA-based 10GbE switch that implements the four optimizers demonstrate that these optimization algorithms are accelerated by up to 3. 0x and 1. 25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves 98.3% of the 10GbE line rate.

Radiation transfer (RT) is an important physical processes of energy transfer in the form of electromagnetic wave, and ART method is a ray-tracing for computing RT of re-connected photons in the simulation of protogalaxies formation. It requires a heavy computational power and complicated memory accesses which are not suitable to acceleration with GPUs. Here, for the future use of FPGA-in-Cloud, the acceleration of ART method with SDAccel on Xilinx's cost efficient FPGA board KCU1500 was tried. Although the execution time was not reduced compared with the host CPU with various combination of derivatives, the energy consumption was reduced to 1/3.35.

In this paper, we propose an acceleration methodology for deep recurrent neural networks (RNNs) implemented on a multi-FPGA platform called Flow-in-Cloud (FiC). RNNs have been proven effective for modeling temporal sequences, such as human speech and written text. However, the implementation of RNNs on traditional hardware is inefficient due to their long-range dependence and irregular computation patterns. This inefficiency manifests itself in the proportional increase of run time with respect to the number of layers of deep RNNs when running on traditional hardware platforms such as a CPUs. Previous works have mostly focused on the optimization of a single RNN cell. In this work, we take advantage of the multi-FPGA system to demonstrate that we can reduce the run time of deep RNNs from O(k) to O(1).

Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.

The Full Particle-In-Cell (Full-PIC) method is a numerical simulation technique used in the research and development of Hall-thrusters, a propulsion mechanism of satellites. The Japan Aerospace Exploration Agency (JAXA) has been developing a software package called NSRU-Full-PIC for the design of Hall thrusters. Since the numerical simulation of NSRU-Full-PIC requires a large computing power, energy efficient accelerators are essential. However, because of the frequent random memory access and Read-After-Write (RAW) hazard, acceleration with GPUs is difficult. In this paper, we tackle the problems by cooperating a CPU and an FPGA in an ARM-based heterogeneous FPGA accelerator. We use Intel’s mid-range SoC, Arria 10 which embeds floating point DSPs for high performance yet low power numerical computation. Intel FPGA SDK for OpenCL is available in the platform for easy offloading of complex tasks. Heavy load processes in NSRU-Full-PIC are implemented with a hardware/software co-design on Arria 10 SoC. Our implementation improved the power consumption by 5.66 times compared to the original code on a Xeon E5-2680 v2 2.8 GHz . The total energy consumption was reduced to 88.44% of the Xeon implementation. The target tasks become 3.48 times faster than the original code on an only ARM Cortex-A9 1.5 GHz in Arria 10 SoC, and 2.50 times faster than the implementation using atomic instructions on an NVIDIA K20c GPU.

In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.