Published papers

Providing large storage on Multi-Access Edge (MEC) devices has various advantages: A large amount of bare data that cannot transfer to the cloud without anonymization can be kept easily. Preprocessing in the MEC devices is a hopeful approach for making "well-selected data"for training AI algorithms on the cloud. By distributing big data across numerous base stations, it is possible to prevent data loss during times of disaster. For such purpose, we propose the Trefoil storage subsystem supports cost and power-efficient stand-alone storage by connecting FPGA boards and up to 32 SATA Solid-State Drives (SSDs) directly. We introduced LiteX, an open-source FPGA system integration tool, to design the storage system. Various LiteX IP cores, including soft CPU cores(VexRISCv), memory controllers (LiteDRAM), and FPGA interconnect controllers (LiteICLink), are combined as well as the SATA controller(LiteSATA). We built an example evaluation system and evaluated a storage system's performance and power consumption with multiple SATA disks. Our evaluation results show that the designed SATA system can best use the SATA disk's maximum bandwidth, 569.1MB/sec for write operations and 523.8MB/sec for read operations. Striping data access with multiple disks demonstrates almost no overhead for a read operation, while a slight speed decrease of 4.24MB/sec per unit was observed for the write operation. Only 3W for the disk unit is needed during disk access. As an example application, a quantum computer simulation is briefly introduced.

A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator's performance.

With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation (2n+4. bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates' data transfer pattern, we propose several HLS designs combined with HDL IPs' interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than 35 W in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.

HARK is open-source software for robot auditions, including auditory functions using a microphone array. The primary tasks of robot audition are sound source localization (SSL), sound source separation, and automatic speech recognition of the separated speech. In particular, SSL is the fundamental function among them, which detects the number and position of sound sources. For high-speed yet low-power processing of the SSL, we implement it on an FPGA board with an SoC-type Xilinx Zynq Ultrascale+. Since the whole processing of the SSL is complicated, we off-loaded two core functions, AddCorrelation and Added NormalizeCorrelation, on the hardwired logic. Approximately 295 times and 365 times, performance improvements were achieved compared with software execution.

Object detection and tracking technology are essential in many ways with the increasing demand for remote video conferencing and video surveillance. This paper focuses on a method that combines an object detection method based on a CNN (Convolutional Neural Network) with a motion-vector-based object tracking method in specified frames instead of the whole frame stream. Although this method can improve the throughput with a small memory requirement, it requires 3D image filters to reduce the noise in each motion vector. The immense computing power needed for 3D image filters prevents this method from being popularly used. To address this problem, we propose to implement the technique on an FPGA and offload the filters and CNN engine on the FPGA hardwired logic. We implemented slide window-based image filters on a Zynq Ultrascale+ FPGA board and achieved 23.42 times performance improvement for the median filter and 55.46 times for the average filter, respectively. Considering the resource usage, it appeared that we could implement these 3D image filters design with YOLO on the target FPGA.

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

Gate-based quantum computers, poised to surpass their classical counterparts, drive intense research interest. Emulating quantum systems relies on state vector-type simulators, hampered by soaring memory demands, especially for systems beyond 40 qubits. Our solution called Trefoil system combines multiple FPGAs and SATA disks. Trefoil features a main unit and eight storage subsystems, each with 32 SATA disks, providing 2 PBytes of memory for up to 47 qubits. Sector-level block transfers enable efficient quantum operations such as H, Z, CNOT, and unitary matrices. The results show an H gate for 30 qubits executes in 10 minutes without increased times using parallel processing. Our study advances scalable quantum computing simulations, surmounting memory limitations.

The Continuous-Variable Quantum Key Distribution (CV-QKD) is a groundbreaking technology that enables two parties, Alice and Bob, to share secret cryptographic keys with security guaranteed by the fundamental principle of quantum mechanics. The optical signal's amplitude and phase quadratures are transmitted through a quantum channel and measured by the receiver (Bob). Due to channel noise, loss, and other imperfections, error correction is necessary to ensure both parties share identical raw key bits while minimizing information leakage to potential eavesdroppers (Eve). Non-Binary Low-Density Parity-Check (NB-LDPC) codes are well-suited for CV-QKD because they achieve high reconciliation efficiency, particularly in low-SNR scenarios. However, the intensive computational complexity hinders its further deployment in real-world applications. In this paper, we present an HLS-based decoder system, FPT-EMS (Field-Programmable T-EMS), which consists of six submodules aligning with the construction of the base design, Trellis-Based Extended Min-Sum (T-EMS). After the dedicated design of each submodule considering algorithm properties and FPGA characteristics, we ultimately achieved a 9.36 × speedup compared with ARM cores of the target platform, RFSoC 4x2, at the throughput of 0.89 Mbps over one iteration.

Open source software for robot audition called HARK aims to make 'OpenCV' in audio signal processing, providing comprehensive functions from multichannel audio input to sound localization, sound source separation, and au-tomatic speech recognition. Since each of these HARK modules takes considerable energy when executed on PC, we propose to implement each module on an FPGA board called M-KUBOS connected. Here, we focus on the most computationally expensive function of HARK; the sound source separation, and implement it on a Zynq Ultrascale+ board. More than twice a performance improvement was achieved by using the sound frequency level parallelization in the HLS description compared to the software execution on the Ryzen 3990X64-core server. Power evaluation of the real board showed that the energy consumption is only 1/23.4 of the server.

Many smart city applications such as optimal path planning for multiple transportation robots in factories and warehouses are formulated as highly complex combinatorial optimization problems. Since these problem-solving processes require time-critical control and low energy consumption when executed at the edge of computer networks, a promising approach is to implement high speed solvers on Field Programmable Gate Array (FPGA) by exploiting its parallelism and energy efficiency. Here we focus on a variant of the Multi-Agent Path Finding (MAPF) problem, which is a problem of finding optimal discrete space-time trajectories of the robots that are required to complete transportation requests in a semiconductor fabrication factory as early as possible without colliding with each other. According to our future aim to find a feasible solution to a large-sized problem instance in a distributed manner, the present paper proposes a multi-FPGA implementation of a variant of 'AmoebaSATslim,' which is a bio-inspired parallel search algorithm to search for a solution to the Boolean satisfiability problem (SAT). We design an FPGA cluster that links two FPGA boards to tackle a minimal-sized instance for two robots to transport two packages, where each of the boards is responsible for finding the trajectory of each of the robots. The proposed dual-FPGA implementation handles 22,544 variables and achieves up to approximately 17-fold faster execution speed than its software implemented on an x86-based personal computer.

Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RTlibSGM runs more than 2× faster at a much lower energy cost.

The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people's lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.