Published papers

This paper presents a time-to-digital converter/analog-to-digital-converter (TDC/ADC) hybrid LiDAR system-on-chip (SoC) to realize reliable self-driving systems. The smart accumulation technique (SAT) is proposed to achieve both 200-m and high-pixel-resolution range imaging, which was untrodden with conventional LiDARs. The 'smart' accumulation is realized by a simple object recognition strategy with small circuit overhead. When compared to conventional accumulations, the LiDAR range is enhanced without degrading the pixel resolution. Moreover, a TDC/ADC hybrid architecture is proposed to achieve a wide-distance-range LiDAR with a small silicon area and short-range precision. To minimize the ADC cost, a residue-quantizing noise-shaping (RQNS) SAR ADC is proposed. The prototype LiDAR SoC is fabricated in the 28-nm CMOS technology and integrated into the silicon photomultiplier (SiPM)-based LiDAR system. LiDAR measured with 240 × 96 pixels at 10 frames/s achieves a measurement range of 200 m with a 70-klx direct sunlight: The measurement range is 2 × longer than conventional designs. Furthermore, our LiDAR achieves 4 × higher effective pixel resolution compared to conventional designs using simple accumulation. A 3-D point-cloud image acquired with a real-life environment is presented.

A fully integrated 4 × 4 802.11abgn/ac/ax transceiver system-on-chip (SoC) with integrated interference analyzer and frequency-dependent in-phase and quadrature (IQ) (FD-IQ) calibration is presented. The FD-IQ technique helps meeting the extremely strict IQ imbalance requirement for 1-K quadratic-amplitude modulation (QAM). The pure current-mode TX baseband (BB) improves SNR to better than 50 dB, and a multi-mode local oscillator (LO) distribution circuit provides non-contiguous operation with the error vector magnitude (EVM) of less than -37 dB. The integrated interference analyzer achieves the highly reliable connection in the presence of the undesired signal and hence improves the frequency usage efficiency by identifying the wireless LAN (WLAN) and other signals in the 2G/5G band.

A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to minimize both area and energy consumption of extremely energy-efficient deep neural network (DNN) accelerators, targeting the Internet-of-Things (IoT) edge devices operating with very strict power budgets (e.g., energy harvesting). PMAC consumes significantly less energy than standard fully digital MACs, due to its efficient analog accumulation nature based on gated-ring oscillator (GRO). The architectural analysis of energy-efficient accelerators is performed, and the energy budget analysis is disclosed. Furthermore, theoretical analysis of PMAC is conducted and comparisons with the conventional analog approaches are shown. By exploiting the DNN digital quantization noise, we further improve the PMAC energy efficiency by designing the internal gain. The bidirectional architecture proposed in this paper achieves an area comparable to those of digital MACs and up to a fivefold improvement in power efficiency. Moreover, the system design constraints are relaxed by eliminating the phase error originating in leakage currents. An asynchronous readout technique and a two-step digital-to-time converter (DTC) to enhance system throughput and compact implementation, respectively, are presented for the first time. We also present DNN hardware-software co-training procedures to show further scaling of the PMAC efficiency. Utilizing such techniques, the measured PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( $\Delta V_{\text {in}}$ ) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step.