Published papers
Matsutani, Hiroki
61-80 items (total 90)
Prediction Router: Yet Another Low Latency On-Chip Router Architecture
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
- Publication Title
- Magazine name IEEE International Symposium on High-Performance Computer Architecture (HPCA'09) Start Page 367 - End Page 378 (Publication Date）2009/02）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems
- Author
- Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
- Publication Title
- Magazine name International Conference on Field Programmable Logic and Applications (FPL'08) Start Page 269 - End Page 274 (Publication Date）2008/09）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
A Lightweight Fault-tolerant Mechanism for Network-on-chip
- Author
- Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston
- Publication Title
- Magazine name ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08) Start Page 13 - End Page 22 (Publication Date）2008/05）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
- Publication Title
- Magazine name ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08) Start Page 23 - End Page 32 (Publication Date）2008/05）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
- Publication Title
- Magazine name Asia and South Pacific Design Automation Conference (ASP-DAC'08) Start Page 55 - End Page 60 (Publication Date）2008/01）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
- Publication Title
- Magazine name International Conference on Parallel Processing (ICPP'07) Start Page 1 - End Page 10 (Publication Date）2007/09）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
- Author
- Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
- Publication Title
- Magazine name International Conference on Field Programmable Logic and Applications (FPL'07) Start Page 383 - End Page 388 (Publication Date）2007/08）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
- Publication Title
- Magazine name IEEE International Parallel and Distributed Processing Symposium (IPDPS'07) Start Page 1 - End Page 10 (Publication Date）2007/05）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries
- Author
- Shin Morishima, Hiroki Matsutani
- Publication Title
- Magazine name ACM SIGARCH Computer Architecture News (CAN) Volume 42(Issue 4) Start Page 75 - End Page 80 (Publication Date）2014/09）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (scientific journal)
- Peer-review Status
- With
Skywalk: a Topology for HPC Networks with Low-delay Switches
- Author
- Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
- Publication Title
- Magazine name IEEE International Parallel and Distributed Processing Symposium (IPDPS'14) Start Page 263 - End Page 272 (Publication Date）2014/05）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips
- Author
- Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
- Publication Title
- Magazine name Design, Automation, and Test in Europe Conference (DATE'14) Start Page 1 - End Page 6 (Publication Date）2014/03）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
3-D NoC with Inductive-Coupling Links for Building-Block SiPs
- Author
- Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
- Publication Title
- Magazine name IEEE Transactions on Computers (TC) Volume 63(Issue 3) Start Page 748 - End Page 763 (Publication Date）2014/03）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (scientific journal)
- Peer-review Status
- With
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
- Author
- Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
- Publication Title
- Magazine name IEEE Micro Volume 33(Issue 6) Start Page 6 - End Page 15 (Publication Date）2013/12）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (scientific journal)
- Peer-review Status
- With
Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture
- Author
- Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
- Publication Title
- Magazine name ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13) Start Page 29 - End Page 36 (Publication Date）2013/04）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Layout-conscious Random Topologies for HPC Off-chip Interconnects
- Author
- Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova
- Publication Title
- Magazine name IEEE International Symposium on High-Performance Computer Architecture (HPCA'13) Start Page 484 - End Page 495 (Publication Date）2013/02）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks
- Author
- Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi
- Publication Title
- Magazine name International Conference on Parallel Processing (ICPP'16) Start Page 340 - End Page 349 (Publication Date）2016/08）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches
- Author
- Yuta Tokusashi, Hiroki Matsutani
- Publication Title
- Magazine name IEEE International Symposium on High Performance Interconnects (Hot Interconnects 24) Start Page 60 - End Page 67 (Publication Date）2016/08）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Randomizing Packet Memory Networks for Low-latency Processor-memory Communication
- Author
- Daichi Fujiki, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
- Publication Title
- Magazine name International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16) Start Page 168 - End Page 175 (Publication Date）2016/02）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (international conference proceedings)
- Peer-review Status
- With
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
- Author
- Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
- Publication Title
- Magazine name IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Volume 24(Issue 2) Start Page 493 - End Page 506 (Publication Date）2016/02）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (scientific journal)
- Peer-review Status
- With
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface
- Author
- Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani
- Publication Title
- Magazine name ACM SIGARCH Computer Architecture News (CAN) Volume 43(Issue 4) Start Page 22 - End Page 27 (Publication Date）2015/09）
- Authorship Category
- Joint Work
- Publication Category
- Research paper (scientific journal)
- Peer-review Status
- With